;............................................................................... ; Altium Deigner Constraints File ; Device : XC3S400AN-4FGG400C ; Board : Carte Blanche II ; Project : FPGA Template ; Version : 2.01 - Release ; Engineer: Steven Howell ; Created :12/07/2015 ;............................................................................... ; ; NOTE *** ; Please use the CB2.UCF located under the folder "Vendor Constraints" for any ; other required attributes needed to be included in this design. ; ;............................................................................... ;............................................................................... Record=FileHeader | Id=DXP Constraints v1.0 ;............................................................................... ;---------------------------------------------------------------------------------------------------------------------------------- ; SUPPORTED TARGETS ; ;---------------------------------------------------------------------------------------------------------------------------------- Record=Constraint | TargetKind=Part | TargetId=XC3S400AN-4FGG400C ;---------------------------------------------------------------------------------------------------------------------------------- ; CLOCKS ; ;---------------------------------------------------------------------------------------------------------------------------------- Record=Constraint | TargetKind=Port | TargetId=CLK12M | FPGA_PINNUM=D11 ;---------------------------------------------------------------------------------------------------------------------------------- ; APPLE II BUS ENABLE ; ;---------------------------------------------------------------------------------------------------------------------------------- Record=Constraint | TargetKind=Port | TargetId=ABUS_EN | FPGA_PINNUM=N17 ;---------------------------------------------------------------------------------------------------------------------------------- ; APPLE II BUS IO ; ;---------------------------------------------------------------------------------------------------------------------------------- Record=Constraint | TargetKind=Port | TargetId=ABUS_PHASE0 | FPGA_PINNUM=A9 Record=Constraint | TargetKind=Port | TargetId=ABUS_PHASE1 | FPGA_PINNUM=E10 Record=Constraint | TargetKind=Port | TargetId=ABUS_3M58 | FPGA_PINNUM=D10 Record=Constraint | TargetKind=Port | TargetId=ABUS_7M | FPGA_PINNUM=C10 Record=Constraint | TargetKind=Port | TargetId=ABUS_Q3 | FPGA_PINNUM=A10 Record=Constraint | TargetKind=Port | TargetId=ABUS_D0 | FPGA_PINNUM=H19 Record=Constraint | TargetKind=Port | TargetId=ABUS_D1 | FPGA_PINNUM=J17 Record=Constraint | TargetKind=Port | TargetId=ABUS_D2 | FPGA_PINNUM=G17 Record=Constraint | TargetKind=Port | TargetId=ABUS_D3 | FPGA_PINNUM=G18 Record=Constraint | TargetKind=Port | TargetId=ABUS_D4 | FPGA_PINNUM=F20 Record=Constraint | TargetKind=Port | TargetId=ABUS_D5 | FPGA_PINNUM=F17 Record=Constraint | TargetKind=Port | TargetId=ABUS_D6 | FPGA_PINNUM=E20 Record=Constraint | TargetKind=Port | TargetId=ABUS_D7 | FPGA_PINNUM=D16 Record=Constraint | TargetKind=Port | TargetId=ABUS_A0 | FPGA_PINNUM=H18 Record=Constraint | TargetKind=Port | TargetId=ABUS_A1 | FPGA_PINNUM=H17 Record=Constraint | TargetKind=Port | TargetId=ABUS_A2 | FPGA_PINNUM=G20 Record=Constraint | TargetKind=Port | TargetId=ABUS_A3 | FPGA_PINNUM=G16 Record=Constraint | TargetKind=Port | TargetId=ABUS_A4 | FPGA_PINNUM=F19 Record=Constraint | TargetKind=Port | TargetId=ABUS_A5 | FPGA_PINNUM=F18 Record=Constraint | TargetKind=Port | TargetId=ABUS_A6 | FPGA_PINNUM=F16 Record=Constraint | TargetKind=Port | TargetId=ABUS_A7 | FPGA_PINNUM=E19 Record=Constraint | TargetKind=Port | TargetId=ABUS_A8 | FPGA_PINNUM=D20 Record=Constraint | TargetKind=Port | TargetId=ABUS_A9 | FPGA_PINNUM=D18 Record=Constraint | TargetKind=Port | TargetId=ABUS_A10 | FPGA_PINNUM=C19 Record=Constraint | TargetKind=Port | TargetId=ABUS_A11 | FPGA_PINNUM=B20 Record=Constraint | TargetKind=Port | TargetId=ABUS_A12 | FPGA_PINNUM=B19 Record=Constraint | TargetKind=Port | TargetId=ABUS_A13 | FPGA_PINNUM=D17 Record=Constraint | TargetKind=Port | TargetId=ABUS_A14 | FPGA_PINNUM=A16 Record=Constraint | TargetKind=Port | TargetId=ABUS_A15 | FPGA_PINNUM=A18 Record=Constraint | TargetKind=Port | TargetId=ABUS_RW | FPGA_PINNUM=C16 Record=Constraint | TargetKind=Port | TargetId=ABUS_IO_SEL | FPGA_PINNUM=H20 Record=Constraint | TargetKind=Port | TargetId=ABUS_IOSTROBE | FPGA_PINNUM=C17 Record=Constraint | TargetKind=Port | TargetId=ABUS_DEV_SEL | FPGA_PINNUM=E18 Record=Constraint | TargetKind=Port | TargetId=ABUS_INTOUT | FPGA_PINNUM=F13 Record=Constraint | TargetKind=Port | TargetId=ABUS_INTIN | FPGA_PINNUM=F14 Record=Constraint | TargetKind=Port | TargetId=ABUS_DMA | FPGA_PINNUM=A17 Record=Constraint | TargetKind=Port | TargetId=ABUS_DMAOUT | FPGA_PINNUM=E13 Record=Constraint | TargetKind=Port | TargetId=ABUS_DMAIN | FPGA_PINNUM=E14 Record=Constraint | TargetKind=Port | TargetId=ABUS_RDY | FPGA_PINNUM=B17 Record=Constraint | TargetKind=Port | TargetId=ABUS_INH | FPGA_PINNUM=C15 Record=Constraint | TargetKind=Port | TargetId=ABUS_NMI | FPGA_PINNUM=D14 Record=Constraint | TargetKind=Port | TargetId=ABUS_IRQ | FPGA_PINNUM=D15 Record=Constraint | TargetKind=Port | TargetId=ABUS_SYNC | FPGA_PINNUM=E11 Record=Constraint | TargetKind=Port | TargetId=ABUS_RESET | FPGA_PINNUM=E15 Record=Constraint | TargetKind=Port | TargetId=ABUS_USER1 | FPGA_PINNUM=C20 ;---------------------------------------------------------------------------------------------------------------------------------- ; AUDIO SERVICES ; ;---------------------------------------------------------------------------------------------------------------------------------- Record=Constraint | TargetKind=Port | TargetId=AV_PA_ON | FPGA_PINNUM=P4 Record=Constraint | TargetKind=Port | TargetId=AV_AUD_LEFT | FPGA_PINNUM=B15 Record=Constraint | TargetKind=Port | TargetId=AV_AUD_RIGHT | FPGA_PINNUM=A15 ;---------------------------------------------------------------------------------------------------------------------------------- ; COMMON VIDEO BUS ; ;---------------------------------------------------------------------------------------------------------------------------------- Record=Constraint | TargetKind=Port | TargetId=RED[7..0] | FPGA_PINNUM=C11,C9,B8,C8,A7,B7,C7,A6 Record=Constraint | TargetKind=Port | TargetId=GREEN[7..0] | FPGA_PINNUM=C6,A5,B5,C5,A4,E6,B9,A3 Record=Constraint | TargetKind=Port | TargetId=BLUE[7..0] | FPGA_PINNUM=C1,C2,F6,B2,A2,D4,B3,C4 Record=Constraint | TargetKind=Port | TargetId=VGA_CLK | FPGA_PINNUM=B1 Record=Constraint | TargetKind=Port | TargetId=VGA_HSYNC | FPGA_PINNUM=C14 Record=Constraint | TargetKind=Port | TargetId=VGA_VSYNC | FPGA_PINNUM=C12 ;---------------------------------------------------------------------------------------------------------------------------------- ; LCD ; ;---------------------------------------------------------------------------------------------------------------------------------- Record=Constraint | TargetKind=Port | TargetId=LCD_EN | FPGA_PINNUM=A14 ;---------------------------------------------------------------------------------------------------------------------------------- ; AD7125 VGA ; ;---------------------------------------------------------------------------------------------------------------------------------- Record=Constraint | TargetKind=Port | TargetId=DAC_EN | FPGA_PINNUM=B13 Record=Constraint | TargetKind=Port | TargetId=DAC_SONG | FPGA_PINNUM=C13 ;---------------------------------------------------------------------------------------------------------------------------------- ; TFP410 HDMI ; ;---------------------------------------------------------------------------------------------------------------------------------- Record=Constraint | TargetKind=Port | TargetId=HDMI_EN | FPGA_PINNUM=D3 Record=Constraint | TargetKind=Port | TargetId=CEC | FPGA_PINNUM=M17 Record=Constraint | TargetKind=Port | TargetId=DDC_DAT | FPGA_PINNUM=F4 Record=Constraint | TargetKind=Port | TargetId=DDC_CLK | FPGA_PINNUM=D1 Record=Constraint | TargetKind=Port | TargetId=MSEN | FPGA_PINNUM=G6 ;---------------------------------------------------------------------------------------------------------------------------------- ; USER INTERFACE IO (UIIO) ; ;---------------------------------------------------------------------------------------------------------------------------------- Record=Constraint | TargetKind=Port | TargetId=UIIO_A | FPGA_PINNUM=F12 Record=Constraint | TargetKind=Port | TargetId=UIIO_B | FPGA_PINNUM=B12 Record=Constraint | TargetKind=Port | TargetId=UIIO_C | FPGA_PINNUM=A12 ;---------------------------------------------------------------------------------------------------------------------------------- ; USER INTERFACE IO (UIIO) ; ;---------------------------------------------------------------------------------------------------------------------------------- Record=Constraint | TargetKind=Port | TargetId=USER_LED | FPGA_PINNUM=V4 ;---------------------------------------------------------------------------------------------------------------------------------- ; COMMON MEMORY BUS ; ;---------------------------------------------------------------------------------------------------------------------------------- Record=Constraint | TargetKind=Port | TargetId=MEM_BUS_A0 | FPGA_PINNUM=W6 Record=Constraint | TargetKind=Port | TargetId=MEM_BUS_A1 | FPGA_PINNUM=U7 Record=Constraint | TargetKind=Port | TargetId=MEM_BUS_A2 | FPGA_PINNUM=V6 Record=Constraint | TargetKind=Port | TargetId=MEM_BUS_A3 | FPGA_PINNUM=W3 Record=Constraint | TargetKind=Port | TargetId=MEM_BUS_A4 | FPGA_PINNUM=U4 Record=Constraint | TargetKind=Port | TargetId=MEM_BUS_A5 | FPGA_PINNUM=N2 Record=Constraint | TargetKind=Port | TargetId=MEM_BUS_A6 | FPGA_PINNUM=N1 Record=Constraint | TargetKind=Port | TargetId=MEM_BUS_A7 | FPGA_PINNUM=M3 Record=Constraint | TargetKind=Port | TargetId=MEM_BUS_A8 | FPGA_PINNUM=M2 Record=Constraint | TargetKind=Port | TargetId=MEM_BUS_A9 | FPGA_PINNUM=M1 Record=Constraint | TargetKind=Port | TargetId=MEM_BUS_A10 | FPGA_PINNUM=G5 Record=Constraint | TargetKind=Port | TargetId=MEM_BUS_A11 | FPGA_PINNUM=D2 Record=Constraint | TargetKind=Port | TargetId=MEM_BUS_A12 | FPGA_PINNUM=E3 Record=Constraint | TargetKind=Port | TargetId=MEM_BUS_A13 | FPGA_PINNUM=H4 Record=Constraint | TargetKind=Port | TargetId=MEM_BUS_A14 | FPGA_PINNUM=J6 Record=Constraint | TargetKind=Port | TargetId=MEM_BUS_A15 | FPGA_PINNUM=K2 Record=Constraint | TargetKind=Port | TargetId=MEM_BUS_A16 | FPGA_PINNUM=K4 Record=Constraint | TargetKind=Port | TargetId=MEM_BUS_A17 | FPGA_PINNUM=L3 Record=Constraint | TargetKind=Port | TargetId=MEM_BUS_D0 | FPGA_PINNUM=T1 Record=Constraint | TargetKind=Port | TargetId=MEM_BUS_D1 | FPGA_PINNUM=T2 Record=Constraint | TargetKind=Port | TargetId=MEM_BUS_D2 | FPGA_PINNUM=T3 Record=Constraint | TargetKind=Port | TargetId=MEM_BUS_D3 | FPGA_PINNUM=U1 Record=Constraint | TargetKind=Port | TargetId=MEM_BUS_D4 | FPGA_PINNUM=U3 Record=Constraint | TargetKind=Port | TargetId=MEM_BUS_D5 | FPGA_PINNUM=V1 Record=Constraint | TargetKind=Port | TargetId=MEM_BUS_D6 | FPGA_PINNUM=V2 Record=Constraint | TargetKind=Port | TargetId=MEM_BUS_D7 | FPGA_PINNUM=L1 Record=Constraint | TargetKind=Port | TargetId=MEM_BUS_D8 | FPGA_PINNUM=H2 Record=Constraint | TargetKind=Port | TargetId=MEM_BUS_D9 | FPGA_PINNUM=H3 Record=Constraint | TargetKind=Port | TargetId=MEM_BUS_D10 | FPGA_PINNUM=G3 Record=Constraint | TargetKind=Port | TargetId=MEM_BUS_D11 | FPGA_PINNUM=J2 Record=Constraint | TargetKind=Port | TargetId=MEM_BUS_D12 | FPGA_PINNUM=F1 Record=Constraint | TargetKind=Port | TargetId=MEM_BUS_D13 | FPGA_PINNUM=H6 Record=Constraint | TargetKind=Port | TargetId=MEM_BUS_D14 | FPGA_PINNUM=F2 Record=Constraint | TargetKind=Port | TargetId=MEM_BUS_D15 | FPGA_PINNUM=G4 Record=Constraint | TargetKind=Port | TargetId=MEM_BUS_NWE | FPGA_PINNUM=P3 Record=Constraint | TargetKind=Port | TargetId=MEM_BUS_NBE[1..0] | FPGA_PINNUM=J1,L5 ;---------------------------------------------------------------------------------------------------------------------------------- ; SRAM MEMORY ; ;---------------------------------------------------------------------------------------------------------------------------------- Record=Constraint | TargetKind=Port | TargetId=SRAM_NCS | FPGA_PINNUM=W1 Record=Constraint | TargetKind=Port | TargetId=SRAM_NOE | FPGA_PINNUM=K3 ;---------------------------------------------------------------------------------------------------------------------------------- ; SDRAM MEMORY ; ;---------------------------------------------------------------------------------------------------------------------------------- Record=Constraint | TargetKind=Port | TargetId=SDRAM_NCS | FPGA_PINNUM=J4 Record=Constraint | TargetKind=Port | TargetId=SDRAM_CKE | FPGA_PINNUM=E1 Record=Constraint | TargetKind=Port | TargetId=SDRAM_CLK | FPGA_PINNUM=F3 Record=Constraint | TargetKind=Port | TargetId=SDRAM_NCAS | FPGA_PINNUM=J3 Record=Constraint | TargetKind=Port | TargetId=SDRAM_NRAS | FPGA_PINNUM=J5 ;---------------------------------------------------------------------------------------------------------------------------------- ; COMMON SPI BUS ; ;---------------------------------------------------------------------------------------------------------------------------------- Record=Constraint | TargetKind=Port | TargetId=FPGA_MOSI | FPGA_PINNUM=W12 Record=Constraint | TargetKind=Port | TargetId=FPGA_MISO | FPGA_PINNUM=W18 Record=Constraint | TargetKind=Port | TargetId=FPGA_SPICLK | FPGA_PINNUM=Y19 ;---------------------------------------------------------------------------------------------------------------------------------- ; M25P128 SPI FLASH MEMORY ; ;---------------------------------------------------------------------------------------------------------------------------------- Record=Constraint | TargetKind=Port | TargetId=FLASH_CS | FPGA_PINNUM=Y2 ;---------------------------------------------------------------------------------------------------------------------------------- ; MICROSD/TRANSFLASH ; ;---------------------------------------------------------------------------------------------------------------------------------- Record=Constraint | TargetKind=Port | TargetId=SD_CS | FPGA_PINNUM=W20 Record=Constraint | TargetKind=Port | TargetId=SD_CD | FPGA_PINNUM=G7 Record=Constraint | TargetKind=Port | TargetId=SD_DAT1 | FPGA_PINNUM=Y17 Record=Constraint | TargetKind=Port | TargetId=SD_DAT2 | FPGA_PINNUM=V19 ;---------------------------------------------------------------------------------------------------------------------------------- ; CBII IO SPI ; ;---------------------------------------------------------------------------------------------------------------------------------- Record=Constraint | TargetKind=Port | TargetId=CBIO_SPI_CS | FPGA_PINNUM=U13 ;---------------------------------------------------------------------------------------------------------------------------------- ; STMPE811 TOUCH SCREEN CONTROLLER ; ;---------------------------------------------------------------------------------------------------------------------------------- Record=Constraint | TargetKind=Port | TargetId=TSC_CS | FPGA_PINNUM=F9 Record=Constraint | TargetKind=Port | TargetId=TSC_IRQ | FPGA_PINNUM=G8 ;---------------------------------------------------------------------------------------------------------------------------------- ; FT2232HQ USB CONTROLLER ; ;---------------------------------------------------------------------------------------------------------------------------------- Record=Constraint | TargetKind=Port | TargetId=D0 | FPGA_PINNUM=A8 Record=Constraint | TargetKind=Port | TargetId=D1 | FPGA_PINNUM=Y18 Record=Constraint | TargetKind=Port | TargetId=D2 | FPGA_PINNUM=V17 Record=Constraint | TargetKind=Port | TargetId=D3 | FPGA_PINNUM=B18 Record=Constraint | TargetKind=Port | TargetId=D4 | FPGA_PINNUM=B11 Record=Constraint | TargetKind=Port | TargetId=D5 | FPGA_PINNUM=D6 Record=Constraint | TargetKind=Port | TargetId=D6 | FPGA_PINNUM=F7 Record=Constraint | TargetKind=Port | TargetId=D7 | FPGA_PINNUM=E7 Record=Constraint | TargetKind=Port | TargetId=RD | FPGA_PINNUM=D8 Record=Constraint | TargetKind=Port | TargetId=WR | FPGA_PINNUM=E9 Record=Constraint | TargetKind=Port | TargetId=TXE | FPGA_PINNUM=E8 Record=Constraint | TargetKind=Port | TargetId=RXF | FPGA_PINNUM=F8 Record=Constraint | TargetKind=Port | TargetId=SIWUB | FPGA_PINNUM=D12 Record=Constraint | TargetKind=Port | TargetId=U5VDET | FPGA_PINNUM=J15 ;---------------------------------------------------------------------------------------------------------------------------------- ; CBII IO 3.3V ONLY ; ;---------------------------------------------------------------------------------------------------------------------------------- Record=Constraint | TargetKind=Port | TargetId=IO3V3_00 | FPGA_PINNUM=W14 Record=Constraint | TargetKind=Port | TargetId=IO3V3_01 | FPGA_PINNUM=Y14 Record=Constraint | TargetKind=Port | TargetId=IO3V3_02 | FPGA_PINNUM=V13 Record=Constraint | TargetKind=Port | TargetId=IO3V3_03 | FPGA_PINNUM=W13 Record=Constraint | TargetKind=Port | TargetId=IO3V3_04 | FPGA_PINNUM=Y13 Record=Constraint | TargetKind=Port | TargetId=IO3V3_05 | FPGA_PINNUM=Y12 Record=Constraint | TargetKind=Port | TargetId=IO3V3_06 | FPGA_PINNUM=R12 Record=Constraint | TargetKind=Port | TargetId=IO3V3_07 | FPGA_PINNUM=T12 Record=Constraint | TargetKind=Port | TargetId=IO3V3_08 | FPGA_PINNUM=U10 Record=Constraint | TargetKind=Port | TargetId=IO3V3_09 | FPGA_PINNUM=V9 Record=Constraint | TargetKind=Port | TargetId=IO3V3_10 | FPGA_PINNUM=W8 Record=Constraint | TargetKind=Port | TargetId=IO3V3_11 | FPGA_PINNUM=V8 Record=Constraint | TargetKind=Port | TargetId=IO3V3_12 | FPGA_PINNUM=V7 Record=Constraint | TargetKind=Port | TargetId=IO3V3_13 | FPGA_PINNUM=T10 Record=Constraint | TargetKind=Port | TargetId=IO3V3_14 | FPGA_PINNUM=U9 Record=Constraint | TargetKind=Port | TargetId=IO3V3_15 | FPGA_PINNUM=T8 Record=Constraint | TargetKind=Port | TargetId=IO3V3_16 | FPGA_PINNUM=Y7 Record=Constraint | TargetKind=Port | TargetId=IO3V3_17 | FPGA_PINNUM=T9 Record=Constraint | TargetKind=Port | TargetId=IO3V3_18 | FPGA_PINNUM=R7 Record=Constraint | TargetKind=Port | TargetId=IO3V3_19 | FPGA_PINNUM=T7 Record=Constraint | TargetKind=Port | TargetId=IO3V3_20 | FPGA_PINNUM=U6 Record=Constraint | TargetKind=Port | TargetId=IO3V3_21 | FPGA_PINNUM=U11 Record=Constraint | TargetKind=Port | TargetId=IO3V3_22 | FPGA_PINNUM=Y11 Record=Constraint | TargetKind=Port | TargetId=IO3V3_23 | FPGA_PINNUM=W10 Record=Constraint | TargetKind=Port | TargetId=IO3V3_24 | FPGA_PINNUM=P10 Record=Constraint | TargetKind=Port | TargetId=IO3V3_25 | FPGA_PINNUM=R8 Record=Constraint | TargetKind=Port | TargetId=IO3V3_26 | FPGA_PINNUM=P9 Record=Constraint | TargetKind=Port | TargetId=IO3V3_27 | FPGA_PINNUM=R10 Record=Constraint | TargetKind=Port | TargetId=IO3V3_28 | FPGA_PINNUM=M7 Record=Constraint | TargetKind=Port | TargetId=IO3V3_29 | FPGA_PINNUM=L7 Record=Constraint | TargetKind=Port | TargetId=IO3V3_30 | FPGA_PINNUM=K5 Record=Constraint | TargetKind=Port | TargetId=IO3V3_31 | FPGA_PINNUM=L6 ;---------------------------------------------------------------------------------------------------------------------------------- ; CBII IO 3.3V AND 5V ; ;---------------------------------------------------------------------------------------------------------------------------------- Record=Constraint | TargetKind=Port | TargetId=IO5V0_00 | FPGA_PINNUM=T13 Record=Constraint | TargetKind=Port | TargetId=IO5V0_01 | FPGA_PINNUM=R13 Record=Constraint | TargetKind=Port | TargetId=IO5V0_02 | FPGA_PINNUM=T14 Record=Constraint | TargetKind=Port | TargetId=IO5V0_03 | FPGA_PINNUM=U15 Record=Constraint | TargetKind=Port | TargetId=IO5V0_04 | FPGA_PINNUM=T15 Record=Constraint | TargetKind=Port | TargetId=IO5V0_05 | FPGA_PINNUM=U16 Record=Constraint | TargetKind=Port | TargetId=IO5V0_06 | FPGA_PINNUM=V16 Record=Constraint | TargetKind=Port | TargetId=IO5V0_07 | FPGA_PINNUM=V15 Record=Constraint | TargetKind=Port | TargetId=IO5V0_08 | FPGA_PINNUM=Y6 Record=Constraint | TargetKind=Port | TargetId=IO5V0_09 | FPGA_PINNUM=W2 Record=Constraint | TargetKind=Port | TargetId=IO5V0_10 | FPGA_PINNUM=U5 Record=Constraint | TargetKind=Port | TargetId=IO5V0_11 | FPGA_PINNUM=R4 Record=Constraint | TargetKind=Port | TargetId=IO5V0_12 | FPGA_PINNUM=R5 Record=Constraint | TargetKind=Port | TargetId=IO5V0_13 | FPGA_PINNUM=R2 Record=Constraint | TargetKind=Port | TargetId=IO5V0_14 | FPGA_PINNUM=T4 Record=Constraint | TargetKind=Port | TargetId=IO5V0_15 | FPGA_PINNUM=T6 Record=Constraint | TargetKind=Port | TargetId=IO5V0_16 | FPGA_PINNUM=V5 Record=Constraint | TargetKind=Port | TargetId=IO5V0_17 | FPGA_PINNUM=Y3 Record=Constraint | TargetKind=Port | TargetId=IO5V0_18 | FPGA_PINNUM=Y4 Record=Constraint | TargetKind=Port | TargetId=IO5V0_19 | FPGA_PINNUM=W4 Record=Constraint | TargetKind=Port | TargetId=IO5V0_20 | FPGA_PINNUM=Y5 Record=Constraint | TargetKind=Port | TargetId=IO5V0_21 | FPGA_PINNUM=W9 Record=Constraint | TargetKind=Port | TargetId=IO5V0_22 | FPGA_PINNUM=Y9 Record=Constraint | TargetKind=Port | TargetId=IO5V0_23 | FPGA_PINNUM=V10 Record=Constraint | TargetKind=Port | TargetId=IO5V0_24 | FPGA_PINNUM=M6 Record=Constraint | TargetKind=Port | TargetId=IO5V0_25 | FPGA_PINNUM=P6 Record=Constraint | TargetKind=Port | TargetId=IO5V0_26 | FPGA_PINNUM=M8 Record=Constraint | TargetKind=Port | TargetId=IO5V0_27 | FPGA_PINNUM=P8 Record=Constraint | TargetKind=Port | TargetId=IO5V0_28 | FPGA_PINNUM=N6 Record=Constraint | TargetKind=Port | TargetId=IO5V0_29 | FPGA_PINNUM=P5 Record=Constraint | TargetKind=Port | TargetId=IO5V0_30 | FPGA_PINNUM=N7 Record=Constraint | TargetKind=Port | TargetId=IO5V0_31 | FPGA_PINNUM=P7 ;---------------------------------------------------------------------------------------------------------------------------------- ; ZERO INSERTION FORCE 48 PIN IO ; ;---------------------------------------------------------------------------------------------------------------------------------- Record=Constraint | TargetKind=Port | TargetId=TT_PIN1 | FPGA_PINNUM=Y16 Record=Constraint | TargetKind=Port | TargetId=TT_PIN2 | FPGA_PINNUM=W16 Record=Constraint | TargetKind=Port | TargetId=TT_PIN3 | FPGA_PINNUM=U17 Record=Constraint | TargetKind=Port | TargetId=TT_PIN4 | FPGA_PINNUM=Y15 Record=Constraint | TargetKind=Port | TargetId=TT_PIN05_01 | FPGA_PINNUM=T17 Record=Constraint | TargetKind=Port | TargetId=TT_PIN06_02 | FPGA_PINNUM=R16 Record=Constraint | TargetKind=Port | TargetId=TT_PIN07_03 | FPGA_PINNUM=T20 Record=Constraint | TargetKind=Port | TargetId=TT_PIN08_04 | FPGA_PINNUM=R17 Record=Constraint | TargetKind=Port | TargetId=TT_PIN09_05 | FPGA_PINNUM=M19 Record=Constraint | TargetKind=Port | TargetId=TT_PIN10_06 | FPGA_PINNUM=N19 Record=Constraint | TargetKind=Port | TargetId=TT_PIN11_07 | FPGA_PINNUM=M20 Record=Constraint | TargetKind=Port | TargetId=TT_PIN12_08 | FPGA_PINNUM=L19 Record=Constraint | TargetKind=Port | TargetId=TT_PIN13_09 | FPGA_PINNUM=L16 Record=Constraint | TargetKind=Port | TargetId=TT_PIN14_10 | FPGA_PINNUM=K20 Record=Constraint | TargetKind=Port | TargetId=TT_PIN15_11 | FPGA_PINNUM=K16 Record=Constraint | TargetKind=Port | TargetId=TT_PIN16_12 | FPGA_PINNUM=J19 Record=Constraint | TargetKind=Port | TargetId=TT_PIN17_13 | FPGA_PINNUM=N18 Record=Constraint | TargetKind=Port | TargetId=TT_PIN18_14 | FPGA_PINNUM=M18 Record=Constraint | TargetKind=Port | TargetId=TT_PIN19_15 | FPGA_PINNUM=L15 Record=Constraint | TargetKind=Port | TargetId=TT_PIN20_16 | FPGA_PINNUM=L18 Record=Constraint | TargetKind=Port | TargetId=TT_PIN21_17 | FPGA_PINNUM=L17 Record=Constraint | TargetKind=Port | TargetId=TT_PIN22_18 | FPGA_PINNUM=K18 Record=Constraint | TargetKind=Port | TargetId=TT_PIN23_19 | FPGA_PINNUM=J20 Record=Constraint | TargetKind=Port | TargetId=TT_PIN24_20 | FPGA_PINNUM=J18 Record=Constraint | TargetKind=Port | TargetId=TT_PIN25_21 | FPGA_PINNUM=R1 Record=Constraint | TargetKind=Port | TargetId=TT_PIN26_22 | FPGA_PINNUM=M5 Record=Constraint | TargetKind=Port | TargetId=TT_PIN27_23 | FPGA_PINNUM=P1 Record=Constraint | TargetKind=Port | TargetId=TT_PIN28_24 | FPGA_PINNUM=M4 Record=Constraint | TargetKind=Port | TargetId=TT_PIN29_25 | FPGA_PINNUM=N4 Record=Constraint | TargetKind=Port | TargetId=TT_PIN30_26 | FPGA_PINNUM=N3 Record=Constraint | TargetKind=Port | TargetId=TT_PIN31_27 | FPGA_PINNUM=R3 Record=Constraint | TargetKind=Port | TargetId=TT_PIN32_28 | FPGA_PINNUM=G1 Record=Constraint | TargetKind=Port | TargetId=TT_PIN33_29 | FPGA_PINNUM=N15 Record=Constraint | TargetKind=Port | TargetId=TT_PIN34_30 | FPGA_PINNUM=P17 Record=Constraint | TargetKind=Port | TargetId=TT_PIN35_31 | FPGA_PINNUM=P16 Record=Constraint | TargetKind=Port | TargetId=TT_PIN36_32 | FPGA_PINNUM=P20 Record=Constraint | TargetKind=Port | TargetId=TT_PIN37_33 | FPGA_PINNUM=R20 Record=Constraint | TargetKind=Port | TargetId=TT_PIN38_34 | FPGA_PINNUM=V11 Record=Constraint | TargetKind=Port | TargetId=TT_PIN39_35 | FPGA_PINNUM=R19 Record=Constraint | TargetKind=Port | TargetId=TT_PIN40_36 | FPGA_PINNUM=R18 Record=Constraint | TargetKind=Port | TargetId=TT_PIN41_37 | FPGA_PINNUM=V12 Record=Constraint | TargetKind=Port | TargetId=TT_PIN42_38 | FPGA_PINNUM=T18 Record=Constraint | TargetKind=Port | TargetId=TT_PIN43_39 | FPGA_PINNUM=U20 Record=Constraint | TargetKind=Port | TargetId=TT_PIN44_40 | FPGA_PINNUM=U19 Record=Constraint | TargetKind=Port | TargetId=TT_PIN45 | FPGA_PINNUM=U18 Record=Constraint | TargetKind=Port | TargetId=TT_PIN46 | FPGA_PINNUM=V20 Record=Constraint | TargetKind=Port | TargetId=TT_PIN47 | FPGA_PINNUM=P18 Record=Constraint | TargetKind=Port | TargetId=TT_PIN48 | FPGA_PINNUM=V14 ;----------------------------------------------------------------------------------------------------------------------------------