Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 

 
Software Version and Target Device
Product Version: ISE:12.1 (WebPack) - M.53d Target Family: Spartan3A and Spartan3AN
OS Platform: NT Target Device: xc3s400an
Project ID (random number) 684acf2150724198a130877b888bb684.ec41281c8f794e5e8377623078a2d249.2 Target Package: fgg400
Registration ID 176036481_0_0_631 Target Speed: -4
Date Generated 2015-07-11T23:13:14 Tool Flow CommandLine
 
User Environment
OS Name Microsoft Windows XP Professional OS Release Service Pack 3 (build 2600)
CPU Name Intel(R) Xeon(R) CPU W3520 @ 2.67GHz CPU Speed 2666 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
  MiscellaneousStatistics
  • AGG_BONDED_IO=50
  • AGG_IO=50
  • AGG_SLICE=2904
  • NUM_4_INPUT_LUT=4784
  • NUM_BONDED_IBUF=4
  • NUM_BONDED_IOB=46
  • NUM_BUFGMUX=9
  • NUM_CYMUX=720
  • NUM_DCM=3
  • NUM_DP_RAM=256
  • NUM_IOB_FF=70
  • NUM_LUT_RT=288
  • NUM_MULT18X18SIO=2
  • NUM_MULTAND=39
  • NUM_RAMB16BWE=16
  • NUM_SLICEL=2776
  • NUM_SLICEM=128
  • NUM_SLICE_FF=2408
  • NUM_XOR=651
NetStatistics
  • NumNets_Active=5884
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BRAMADDR=416
  • NumNodesOfType_Active_BRAMDUMMY=280
  • NumNodesOfType_Active_CLKPIN=1697
  • NumNodesOfType_Active_CNTRLPIN=2555
  • NumNodesOfType_Active_DOUBLE=17552
  • NumNodesOfType_Active_DUMMY=14954
  • NumNodesOfType_Active_DUMMYBANK=271
  • NumNodesOfType_Active_DUMMYESC=4
  • NumNodesOfType_Active_GLOBAL=303
  • NumNodesOfType_Active_HFULLHEX=325
  • NumNodesOfType_Active_HLONG=79
  • NumNodesOfType_Active_HUNIHEX=2105
  • NumNodesOfType_Active_INPUT=17092
  • NumNodesOfType_Active_IOBOUTPUT=20
  • NumNodesOfType_Active_OMUX=5345
  • NumNodesOfType_Active_OUTPUT=5668
  • NumNodesOfType_Active_PREBXBY=4420
  • NumNodesOfType_Active_VFULLHEX=1502
  • NumNodesOfType_Active_VLONG=296
  • NumNodesOfType_Active_VUNIHEX=2434
  • NumNodesOfType_Gnd_BRAMDUMMY=130
  • NumNodesOfType_Gnd_CLKPIN=1
  • NumNodesOfType_Gnd_CNTRLPIN=4
  • NumNodesOfType_Gnd_DOUBLE=44
  • NumNodesOfType_Gnd_DUMMY=2
  • NumNodesOfType_Gnd_DUMMYBANK=11
  • NumNodesOfType_Gnd_HUNIHEX=2
  • NumNodesOfType_Gnd_INPUT=175
  • NumNodesOfType_Gnd_OMUX=55
  • NumNodesOfType_Gnd_OUTPUT=37
  • NumNodesOfType_Gnd_PREBXBY=43
  • NumNodesOfType_Gnd_VFULLHEX=16
  • NumNodesOfType_Gnd_VLONG=2
  • NumNodesOfType_Gnd_VUNIHEX=2
  • NumNodesOfType_Vcc_BRAMDUMMY=2
  • NumNodesOfType_Vcc_CLKPIN=2
  • NumNodesOfType_Vcc_CNTRLPIN=13
  • NumNodesOfType_Vcc_DUMMYBANK=6
  • NumNodesOfType_Vcc_INPUT=12
  • NumNodesOfType_Vcc_PREBXBY=7
  • NumNodesOfType_Vcc_VCCOUT=17
SiteStatistics
  • IBUF-DIFFMTB=2
  • IBUF-DIFFSTB=2
  • IOB-DIFFMLR=20
  • IOB-DIFFMTB=4
  • IOB-DIFFSLR=19
  • IOB-DIFFSTB=3
  • SLICEL-SLICEM=1315
SiteSummary
  • BUFGMUX=9
  • BUFGMUX_GCLKMUX=9
  • BUFGMUX_GCLK_BUFFER=9
  • DCM=3
  • DCM_DCM=3
  • IBUF=4
  • IBUF_DELAY_ADJ_BBOX=4
  • IBUF_INBUF=4
  • IBUF_PAD=4
  • IOB=46
  • IOB_DELAY_ADJ_BBOX=16
  • IOB_IFF1=16
  • IOB_INBUF=16
  • IOB_OFF1=38
  • IOB_OUTBUF=46
  • IOB_PAD=46
  • IOB_TFF1=16
  • MULT18X18SIO=2
  • MULT18X18SIO_MULT18X18SIO=2
  • RAMB16BWE=16
  • RAMB16BWE_RAMB16BWE=16
  • SLICEL=2776
  • SLICEL_C1VDD=12
  • SLICEL_C2VDD=10
  • SLICEL_CYMUXF=368
  • SLICEL_CYMUXG=352
  • SLICEL_F=2283
  • SLICEL_F5MUX=262
  • SLICEL_F6MUX=7
  • SLICEL_FAND=20
  • SLICEL_FFX=1303
  • SLICEL_FFY=1105
  • SLICEL_G=2245
  • SLICEL_GAND=19
  • SLICEL_GNDF=248
  • SLICEL_GNDG=237
  • SLICEL_XORF=326
  • SLICEL_XORG=325
  • SLICEM=128
  • SLICEM_F=128
  • SLICEM_G=128
  • SLICEM_WSGEN=128
 
Configuration Data
BUFGMUX
  • S=[S_INV:9] [S:0]
BUFGMUX_GCLKMUX
  • DISABLE_ATTR=[LOW:9]
  • S=[S_INV:9] [S:0]
DCM
  • PSCLK=[PSCLK_INV:2] [PSCLK:1]
  • PSEN=[PSEN_INV:2] [PSEN:1]
  • PSINCDEC=[PSINCDEC_INV:2] [PSINCDEC:1]
  • RST=[RST:3] [RST_INV:0]
DCM_DCM
  • CLKDV_DIVIDE=[2:2] [16:1]
  • CLKOUT_PHASE_SHIFT=[NONE:3]
  • CLK_FEEDBACK=[1X:3]
  • DESKEW_ADJUST=[9:3]
  • DFS_FREQUENCY_MODE=[LOW:3]
  • DLL_FREQUENCY_MODE=[LOW:3]
  • DUTY_CYCLE_CORRECTION=[TRUE:3]
  • FACTORY_JF1=[0XC0:3]
  • FACTORY_JF2=[0X80:3]
  • PSCLK=[PSCLK_INV:2] [PSCLK:1]
  • PSEN=[PSEN_INV:2] [PSEN:1]
  • PSINCDEC=[PSINCDEC_INV:2] [PSINCDEC:1]
  • RST=[RST:3] [RST_INV:0]
IBUF_DELAY_ADJ_BBOX
  • DELAY_ADJ_ATTRBOX=[FIXED:4]
  • IBUF_DELAY_VALUE=[DLY0:4]
  • IFD_DELAY_VALUE=[DLY0:4]
  • SEL_IN=[SEL_IN:4] [SEL_IN_INV:0]
IBUF_PAD
  • IOATTRBOX=[LVCMOS25:4]
IOB
  • ICE=[ICE:16] [ICE_INV:0]
  • ICLK1=[ICLK1_INV:0] [ICLK1:16]
  • O1=[O1_INV:0] [O1:46]
  • OCE=[OCE:0] [OCE_INV:15]
  • OTCLK1=[OTCLK1_INV:0] [OTCLK1:38]
  • SR=[SR:0] [SR_INV:37]
  • T1=[T1_INV:0] [T1:16]
IOB_DELAY_ADJ_BBOX
  • DELAY_ADJ_ATTRBOX=[FIXED:16]
  • IBUF_DELAY_VALUE=[DLY0:16]
  • IFD_DELAY_VALUE=[DLY5:16]
  • SEL_IN=[SEL_IN:16] [SEL_IN_INV:0]
IOB_IFF1
  • CE=[CE:16] [CE_INV:0]
  • CK=[CK:16] [CK_INV:0]
  • IFF1_INIT_ATTR=[INIT0:16]
  • IFF1_SR_ATTR=[SRLOW:16]
  • IFFATTRBOX=[SYNC:16]
  • LATCH_OR_FF=[FF:16]
  • SR=[SR:0] [SR_INV:16]
IOB_OFF1
  • CE=[CE:0] [CE_INV:15]
  • CK=[CK:38] [CK_INV:0]
  • D=[D:38] [D_INV:0]
  • LATCH_OR_FF=[FF:38]
  • OFF1_INIT_ATTR=[INIT0:1] [INIT1:37]
  • OFF1_SR_ATTR=[SRHIGH:37]
  • OFFATTRBOX=[SYNC:37]
  • SR=[SR:0] [SR_INV:37]
IOB_OUTBUF
  • IN=[IN_INV:0] [IN:46]
  • SUSPEND=[3STATE:46]
  • TRI=[TRI_INV:0] [TRI:16]
IOB_PAD
  • DRIVEATTRBOX=[12:46]
  • IOATTRBOX=[LVCMOS25:46]
  • SLEW=[SLOW:46]
IOB_TFF1
  • CK=[CK:16] [CK_INV:0]
  • D=[D:16] [D_INV:0]
  • LATCH_OR_FF=[FF:16]
  • SR=[SR:0] [SR_INV:16]
  • TFF1_INIT_ATTR=[INIT1:16]
  • TFF1_SR_ATTR=[SRHIGH:16]
  • TFFATTRBOX=[SYNC:16]
MULT18X18SIO
  • CEA=[CEA_INV:0] [CEA:2]
  • CEB=[CEB_INV:0] [CEB:2]
  • CEP=[CEP:2] [CEP_INV:0]
  • CLK=[CLK:2] [CLK_INV:0]
  • RSTA=[RSTA:2] [RSTA_INV:0]
  • RSTB=[RSTB:2] [RSTB_INV:0]
  • RSTP=[RSTP_INV:0] [RSTP:2]
MULT18X18SIO_MULT18X18SIO
  • AREG=[1:2]
  • BREG=[1:2]
  • B_INPUT=[DIRECT:2]
  • CEA=[CEA_INV:0] [CEA:2]
  • CEB=[CEB_INV:0] [CEB:2]
  • CEP=[CEP:2] [CEP_INV:0]
  • CLK=[CLK:2] [CLK_INV:0]
  • PREG=[0:2]
  • PREG_CLKINVERSION=[0:2]
  • RSTA=[RSTA:2] [RSTA_INV:0]
  • RSTB=[RSTB:2] [RSTB_INV:0]
  • RSTP=[RSTP_INV:0] [RSTP:2]
RAMB16BWE
  • CLKA=[CLKA_INV:0] [CLKA:16]
  • CLKB=[CLKB_INV:0] [CLKB:16]
  • ENA=[ENA_INV:0] [ENA:16]
  • ENB=[ENB_INV:0] [ENB:16]
  • SSRA=[SSRA_INV:0] [SSRA:16]
  • SSRB=[SSRB_INV:0] [SSRB:16]
  • WEA0=[WEA0:16] [WEA0_INV:0]
  • WEA1=[WEA1:16] [WEA1_INV:0]
  • WEA2=[WEA2:16] [WEA2_INV:0]
  • WEA3=[WEA3_INV:0] [WEA3:16]
  • WEB0=[WEB0:16] [WEB0_INV:0]
  • WEB1=[WEB1:16] [WEB1_INV:0]
  • WEB2=[WEB2_INV:0] [WEB2:16]
  • WEB3=[WEB3:16] [WEB3_INV:0]
RAMB16BWE_RAMB16BWE
  • CLKA=[CLKA_INV:0] [CLKA:16]
  • CLKB=[CLKB_INV:0] [CLKB:16]
  • DATA_WIDTH_A=[2:16]
  • DATA_WIDTH_B=[2:16]
  • ENA=[ENA_INV:0] [ENA:16]
  • ENB=[ENB_INV:0] [ENB:16]
  • SSRA=[SSRA_INV:0] [SSRA:16]
  • SSRB=[SSRB_INV:0] [SSRB:16]
  • WEA0=[WEA0:16] [WEA0_INV:0]
  • WEA1=[WEA1:16] [WEA1_INV:0]
  • WEA2=[WEA2:16] [WEA2_INV:0]
  • WEA3=[WEA3_INV:0] [WEA3:16]
  • WEB0=[WEB0:16] [WEB0_INV:0]
  • WEB1=[WEB1:16] [WEB1_INV:0]
  • WEB2=[WEB2_INV:0] [WEB2:16]
  • WEB3=[WEB3:16] [WEB3_INV:0]
  • WRITE_MODE_A=[WRITE_FIRST:16]
  • WRITE_MODE_B=[WRITE_FIRST:16]
SLICEL
  • BX=[BX_INV:1] [BX:654]
  • BY=[BY:446] [BY_INV:10]
  • CE=[CE:1103] [CE_INV:11]
  • CIN=[CIN_INV:0] [CIN:349]
  • CLK=[CLK:1470] [CLK_INV:5]
  • SR=[SR:1014] [SR_INV:214]
SLICEL_CYMUXF
  • 0=[0:368] [0_INV:0]
  • 1=[1_INV:1] [1:367]
SLICEL_CYMUXG
  • 0=[0:352] [0_INV:0]
SLICEL_F5MUX
  • S0=[S0:262] [S0_INV:0]
SLICEL_F6MUX
  • S0=[S0:7] [S0_INV:0]
SLICEL_FFX
  • CE=[CE:1005] [CE_INV:9]
  • CK=[CK:1300] [CK_INV:3]
  • D=[D:1303] [D_INV:0]
  • FFX_INIT_ATTR=[INIT0:1255] [INIT1:48]
  • FFX_SR_ATTR=[SRLOW:1265] [SRHIGH:38]
  • LATCH_OR_FF=[FF:1303]
  • REV=[REV_INV:0] [REV:3]
  • SR=[SR:934] [SR_INV:154]
  • SYNC_ATTR=[ASYNC:225] [SYNC:1078]
SLICEL_FFY
  • CE=[CE:857] [CE_INV:9]
  • CK=[CK:1101] [CK_INV:4]
  • D=[D:1095] [D_INV:10]
  • FFY_INIT_ATTR=[INIT0:1040] [INIT1:65]
  • FFY_SR_ATTR=[SRLOW:1045] [SRHIGH:60]
  • LATCH_OR_FF=[FF:1105]
  • REV=[REV_INV:0] [REV:1]
  • SR=[SR:693] [SR_INV:184]
  • SYNC_ATTR=[ASYNC:242] [SYNC:863]
SLICEL_XORF
  • 1=[1_INV:1] [1:325]
SLICEM
  • BY=[BY:128] [BY_INV:0]
  • CLK=[CLK:128] [CLK_INV:0]
  • SR=[SR:128] [SR_INV:0]
SLICEM_F
  • DI=[DI:128] [DI_INV:0]
  • F_ATTR=[DUAL_PORT:128]
  • LUT_OR_MEM=[RAM:128]
SLICEM_G
  • DI=[DI:128] [DI_INV:0]
  • G_ATTR=[DUAL_PORT:128]
  • LUT_OR_MEM=[RAM:128]
SLICEM_WSGEN
  • CK=[CK:128] [CK_INV:0]
  • WE=[WE_INV:0] [WE:128]
 
Pin Data
BUFGMUX
  • I0=9
  • O=9
  • S=9
BUFGMUX_GCLKMUX
  • I0=9
  • OUT=9
  • S=9
BUFGMUX_GCLK_BUFFER
  • IN=9
  • OUT=9
DCM
  • CLK0=3
  • CLKDV=1
  • CLKFB=3
  • CLKFX=2
  • CLKIN=3
  • LOCKED=3
  • PSCLK=3
  • PSEN=3
  • PSINCDEC=3
  • RST=3
  • STATUS2=2
DCM_DCM
  • CLK0=3
  • CLKDV=1
  • CLKFB=3
  • CLKFX=2
  • CLKIN=3
  • LOCKED=3
  • PSCLK=3
  • PSEN=3
  • PSINCDEC=3
  • RST=3
  • STATUS2=2
IBUF
  • I=4
  • PAD=4
IBUF_DELAY_ADJ_BBOX
  • IBUF_OUT=4
  • SEL_IN=4
IBUF_INBUF
  • IN=4
  • OUT=4
IBUF_PAD
  • PAD=4
IOB
  • ICE=16
  • ICLK1=16
  • IQ1=16
  • O1=46
  • OCE=15
  • OTCLK1=38
  • PAD=46
  • SR=37
  • T1=16
IOB_DELAY_ADJ_BBOX
  • IFD_OUT=16
  • SEL_IN=16
IOB_IFF1
  • CE=16
  • CK=16
  • D=16
  • Q=16
  • SR=16
IOB_INBUF
  • IN=16
  • OUT=16
IOB_OFF1
  • CE=15
  • CK=38
  • D=38
  • Q=38
  • SR=37
IOB_OUTBUF
  • IN=46
  • OUT=46
  • TRI=16
IOB_PAD
  • PAD=46
IOB_TFF1
  • CK=16
  • D=16
  • Q=16
  • SR=16
MULT18X18SIO
  • A0=2
  • A1=2
  • A10=2
  • A11=2
  • A12=2
  • A13=2
  • A14=2
  • A15=2
  • A16=2
  • A17=2
  • A2=2
  • A3=2
  • A4=2
  • A5=2
  • A6=2
  • A7=2
  • A8=2
  • A9=2
  • B0=2
  • B1=2
  • B10=2
  • B11=2
  • B12=2
  • B13=2
  • B14=2
  • B15=2
  • B16=2
  • B17=2
  • B2=2
  • B3=2
  • B4=2
  • B5=2
  • B6=2
  • B7=2
  • B8=2
  • B9=2
  • CEA=2
  • CEB=2
  • CEP=2
  • CLK=2
  • P0=2
  • P1=2
  • P10=2
  • P11=2
  • P12=2
  • P13=2
  • P14=2
  • P15=2
  • P16=2
  • P17=2
  • P18=2
  • P19=1
  • P2=2
  • P20=1
  • P3=2
  • P4=2
  • P5=2
  • P6=2
  • P7=2
  • P8=2
  • P9=2
  • RSTA=2
  • RSTB=2
  • RSTP=2
MULT18X18SIO_MULT18X18SIO
  • A0=2
  • A1=2
  • A10=2
  • A11=2
  • A12=2
  • A13=2
  • A14=2
  • A15=2
  • A16=2
  • A17=2
  • A2=2
  • A3=2
  • A4=2
  • A5=2
  • A6=2
  • A7=2
  • A8=2
  • A9=2
  • B0=2
  • B1=2
  • B10=2
  • B11=2
  • B12=2
  • B13=2
  • B14=2
  • B15=2
  • B16=2
  • B17=2
  • B2=2
  • B3=2
  • B4=2
  • B5=2
  • B6=2
  • B7=2
  • B8=2
  • B9=2
  • CEA=2
  • CEB=2
  • CEP=2
  • CLK=2
  • P0=2
  • P1=2
  • P10=2
  • P11=2
  • P12=2
  • P13=2
  • P14=2
  • P15=2
  • P16=2
  • P17=2
  • P18=2
  • P19=1
  • P2=2
  • P20=1
  • P3=2
  • P4=2
  • P5=2
  • P6=2
  • P7=2
  • P8=2
  • P9=2
  • RSTA=2
  • RSTB=2
  • RSTP=2
RAMB16BWE
  • ADDRA1=16
  • ADDRA10=16
  • ADDRA11=16
  • ADDRA12=16
  • ADDRA13=16
  • ADDRA2=16
  • ADDRA3=16
  • ADDRA4=16
  • ADDRA5=16
  • ADDRA6=16
  • ADDRA7=16
  • ADDRA8=16
  • ADDRA9=16
  • ADDRB1=16
  • ADDRB10=16
  • ADDRB11=16
  • ADDRB12=16
  • ADDRB13=16
  • ADDRB2=16
  • ADDRB3=16
  • ADDRB4=16
  • ADDRB5=16
  • ADDRB6=16
  • ADDRB7=16
  • ADDRB8=16
  • ADDRB9=16
  • CLKA=16
  • CLKB=16
  • DIB0=16
  • DIB1=16
  • DOA0=16
  • DOA1=16
  • DOB0=16
  • DOB1=16
  • ENA=16
  • ENB=16
  • SSRA=16
  • SSRB=16
  • WEA0=16
  • WEA1=16
  • WEA2=16
  • WEA3=16
  • WEB0=16
  • WEB1=16
  • WEB2=16
  • WEB3=16
RAMB16BWE_RAMB16BWE
  • ADDRA1=16
  • ADDRA10=16
  • ADDRA11=16
  • ADDRA12=16
  • ADDRA13=16
  • ADDRA2=16
  • ADDRA3=16
  • ADDRA4=16
  • ADDRA5=16
  • ADDRA6=16
  • ADDRA7=16
  • ADDRA8=16
  • ADDRA9=16
  • ADDRB1=16
  • ADDRB10=16
  • ADDRB11=16
  • ADDRB12=16
  • ADDRB13=16
  • ADDRB2=16
  • ADDRB3=16
  • ADDRB4=16
  • ADDRB5=16
  • ADDRB6=16
  • ADDRB7=16
  • ADDRB8=16
  • ADDRB9=16
  • CLKA=16
  • CLKB=16
  • DIB0=16
  • DIB1=16
  • DOA0=16
  • DOA1=16
  • DOB0=16
  • DOB1=16
  • ENA=16
  • ENB=16
  • SSRA=16
  • SSRB=16
  • WEA0=16
  • WEA1=16
  • WEA2=16
  • WEA3=16
  • WEB0=16
  • WEB1=16
  • WEB2=16
  • WEB3=16
SLICEL
  • BX=655
  • BY=456
  • CE=1114
  • CIN=349
  • CLK=1475
  • COUT=352
  • F1=2281
  • F2=2093
  • F3=1697
  • F4=929
  • F5=14
  • FXINA=7
  • FXINB=7
  • G1=2240
  • G2=2066
  • G3=1652
  • G4=916
  • SR=1228
  • X=1407
  • XQ=1303
  • Y=1381
  • YQ=1105
SLICEL_C1VDD
  • 1=12
SLICEL_C2VDD
  • 1=10
SLICEL_CYMUXF
  • 0=368
  • 1=368
  • OUT=368
  • S0=368
SLICEL_CYMUXG
  • 0=352
  • 1=352
  • OUT=352
  • S0=352
SLICEL_F
  • A1=2273
  • A2=2093
  • A3=1697
  • A4=929
  • D=2283
SLICEL_F5MUX
  • F=262
  • G=262
  • OUT=262
  • S0=262
SLICEL_F6MUX
  • 0=7
  • 1=7
  • OUT=7
  • S0=7
SLICEL_FAND
  • 0=20
  • 1=20
  • O=20
SLICEL_FFX
  • CE=1014
  • CK=1303
  • D=1303
  • Q=1303
  • REV=3
  • SR=1088
SLICEL_FFY
  • CE=866
  • CK=1105
  • D=1105
  • Q=1105
  • REV=1
  • SR=877
SLICEL_G
  • A1=2231
  • A2=2064
  • A3=1652
  • A4=916
  • D=2245
SLICEL_GAND
  • 0=19
  • 1=19
  • O=19
SLICEL_GNDF
  • 0=248
SLICEL_GNDG
  • 0=237
SLICEL_XORF
  • 0=326
  • 1=326
  • O=326
SLICEL_XORG
  • 0=325
  • 1=325
  • O=325
SLICEM
  • BY=128
  • CLK=128
  • F1=128
  • F2=128
  • F3=128
  • F4=128
  • G1=128
  • G2=128
  • G3=128
  • G4=128
  • SR=128
  • X=128
SLICEM_F
  • A1=128
  • A2=128
  • A3=128
  • A4=128
  • D=128
  • DI=128
  • WF1=128
  • WF2=128
  • WF3=128
  • WF4=128
  • WS=128
SLICEM_G
  • A1=128
  • A2=128
  • A3=128
  • A4=128
  • DI=128
  • WG1=128
  • WG2=128
  • WG3=128
  • WG4=128
  • WS=128
SLICEM_WSGEN
  • CK=128
  • WE=128
  • WSF=128
  • WSG=128
 
Software Quality
Run Statistics
Bitgen 12903 12902 0 0 0 0 0
MAP 7037 6839 0 0 0 0 0
NGDBuild 7354 7338 0 0 0 0 0
PAR 6831 6479 322 0 0 0 0
Start 0 0 0 0 0 0 0
_impact 245 241 0 0 0 0 0
bitgen 1 1 0 0 0 0 0
edif2ngd 74844 74840 0 0 0 0 0
map 14 2 0 0 0 0 0
ngc2edif 140 140 0 0 0 0 0
ngcbuild 117 117 0 0 0 0 0
ngdbuild 17 16 0 0 0 0 0
par 2 2 0 0 0 0 0
trce 6485 6481 0 0 0 0 0
xst 7093 6990 0 0 0 0 0
 
Unisim Statistics
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_AND2=229 NGDBUILD_NUM_AND2B1=240 NGDBUILD_NUM_AND3=8 NGDBUILD_NUM_AND3B1=7
NGDBUILD_NUM_AND3B2=6 NGDBUILD_NUM_AND4B1=1 NGDBUILD_NUM_AND4B2=1 NGDBUILD_NUM_AND4B3=2
NGDBUILD_NUM_BUFG=9 NGDBUILD_NUM_DCM_SP=3 NGDBUILD_NUM_FD=17 NGDBUILD_NUM_FDC=6
NGDBUILD_NUM_FDCE=62 NGDBUILD_NUM_FDCPE=77 NGDBUILD_NUM_FDC_1=4 NGDBUILD_NUM_FDE=287
NGDBUILD_NUM_FDP=12 NGDBUILD_NUM_FDPE=5 NGDBUILD_NUM_FDR=473 NGDBUILD_NUM_FDRE=1490
NGDBUILD_NUM_FDRS=1 NGDBUILD_NUM_FDRSE=3 NGDBUILD_NUM_FDS=95 NGDBUILD_NUM_FDSE=59
NGDBUILD_NUM_GND=26 NGDBUILD_NUM_IBUF=20 NGDBUILD_NUM_INV=24 NGDBUILD_NUM_LUT1=172
NGDBUILD_NUM_LUT1_L=177 NGDBUILD_NUM_LUT2=515 NGDBUILD_NUM_LUT2_L=195 NGDBUILD_NUM_LUT3=975
NGDBUILD_NUM_LUT3_L=743 NGDBUILD_NUM_LUT4=1251 NGDBUILD_NUM_LUT4_L=604 NGDBUILD_NUM_MULT18X18SIO=2
NGDBUILD_NUM_MULT_AND=39 NGDBUILD_NUM_MUXCY=13 NGDBUILD_NUM_MUXCY_L=707 NGDBUILD_NUM_MUXF5=271
NGDBUILD_NUM_MUXF6=7 NGDBUILD_NUM_NAND2=1 NGDBUILD_NUM_NAND3=1 NGDBUILD_NUM_NOR2=3
NGDBUILD_NUM_OBUF=30 NGDBUILD_NUM_OBUFT=16 NGDBUILD_NUM_OR2=134 NGDBUILD_NUM_OR2B1=6
NGDBUILD_NUM_OR3B3=1 NGDBUILD_NUM_OR4=2 NGDBUILD_NUM_OR4B1=1 NGDBUILD_NUM_OR4B4=1
NGDBUILD_NUM_RAMB16BWE=16 NGDBUILD_NUM_VCC=18 NGDBUILD_NUM_XNOR2=14 NGDBUILD_NUM_XORCY=649