Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 

 
Software Version and Target Device
Product Version: ISE:12.1 (WebPack) - M.53d Target Family: Spartan3A and Spartan3AN
OS Platform: NT Target Device: xc3s400an
Project ID (random number) 684acf2150724198a130877b888bb684.1e10391c72fc41cf84f90546105d10c3.2 Target Package: fgg400
Registration ID 176036481_0_0_631 Target Speed: -4
Date Generated 2015-07-11T23:54:26 Tool Flow CommandLine
 
User Environment
OS Name Microsoft Windows XP Professional OS Release Service Pack 3 (build 2600)
CPU Name Intel(R) Xeon(R) CPU W3520 @ 2.67GHz CPU Speed 2666 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
  MiscellaneousStatistics
  • AGG_BONDED_IO=62
  • AGG_IO=62
  • AGG_SLICE=2628
  • NUM_4_INPUT_LUT=4482
  • NUM_BONDED_IBUF=4
  • NUM_BONDED_IOB=58
  • NUM_BUFGMUX=5
  • NUM_CYMUX=671
  • NUM_DCM=2
  • NUM_DP_RAM=256
  • NUM_IOB_FF=16
  • NUM_LUT_RT=244
  • NUM_MULT18X18SIO=2
  • NUM_MULTAND=39
  • NUM_RAMB16BWE=8
  • NUM_SLICEL=2500
  • NUM_SLICEM=128
  • NUM_SLICE_FF=1984
  • NUM_XOR=599
NetStatistics
  • NumNets_Active=5390
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BRAMADDR=192
  • NumNodesOfType_Active_BRAMDUMMY=232
  • NumNodesOfType_Active_CLKPIN=1384
  • NumNodesOfType_Active_CNTRLPIN=2197
  • NumNodesOfType_Active_DOUBLE=15988
  • NumNodesOfType_Active_DUMMY=14138
  • NumNodesOfType_Active_DUMMYBANK=143
  • NumNodesOfType_Active_DUMMYESC=21
  • NumNodesOfType_Active_GLOBAL=242
  • NumNodesOfType_Active_HFULLHEX=336
  • NumNodesOfType_Active_HLONG=50
  • NumNodesOfType_Active_HUNIHEX=1834
  • NumNodesOfType_Active_INPUT=15862
  • NumNodesOfType_Active_IOBOUTPUT=36
  • NumNodesOfType_Active_OMUX=4794
  • NumNodesOfType_Active_OUTPUT=5163
  • NumNodesOfType_Active_PREBXBY=3980
  • NumNodesOfType_Active_VFULLHEX=1276
  • NumNodesOfType_Active_VLONG=251
  • NumNodesOfType_Active_VUNIHEX=2052
  • NumNodesOfType_Gnd_BRAMDUMMY=82
  • NumNodesOfType_Gnd_CLKPIN=1
  • NumNodesOfType_Gnd_CNTRLPIN=2
  • NumNodesOfType_Gnd_DOUBLE=32
  • NumNodesOfType_Gnd_DUMMY=2
  • NumNodesOfType_Gnd_DUMMYBANK=6
  • NumNodesOfType_Gnd_INPUT=95
  • NumNodesOfType_Gnd_OMUX=26
  • NumNodesOfType_Gnd_OUTPUT=20
  • NumNodesOfType_Gnd_PREBXBY=12
  • NumNodesOfType_Gnd_VFULLHEX=7
  • NumNodesOfType_Vcc_BRAMDUMMY=2
  • NumNodesOfType_Vcc_CLKPIN=1
  • NumNodesOfType_Vcc_CNTRLPIN=7
  • NumNodesOfType_Vcc_DUMMYBANK=3
  • NumNodesOfType_Vcc_INPUT=9
  • NumNodesOfType_Vcc_PREBXBY=6
  • NumNodesOfType_Vcc_VCCOUT=12
SiteStatistics
  • IBUF-DIFFMTB=2
  • IBUF-DIFFSTB=2
  • IOB-DIFFMLR=22
  • IOB-DIFFMTB=7
  • IOB-DIFFSLR=23
  • IOB-DIFFSTB=6
  • SLICEL-SLICEM=1157
SiteSummary
  • BUFGMUX=5
  • BUFGMUX_GCLKMUX=5
  • BUFGMUX_GCLK_BUFFER=5
  • DCM=2
  • DCM_DCM=2
  • IBUF=4
  • IBUF_DELAY_ADJ_BBOX=4
  • IBUF_INBUF=4
  • IBUF_PAD=4
  • IOB=58
  • IOB_DELAY_ADJ_BBOX=16
  • IOB_IFF1=16
  • IOB_INBUF=16
  • IOB_OUTBUF=58
  • IOB_PAD=58
  • MULT18X18SIO=2
  • MULT18X18SIO_MULT18X18SIO=2
  • RAMB16BWE=8
  • RAMB16BWE_RAMB16BWE=8
  • SLICEL=2500
  • SLICEL_C1VDD=8
  • SLICEL_C2VDD=7
  • SLICEL_CYMUXF=343
  • SLICEL_CYMUXG=328
  • SLICEL_F=2137
  • SLICEL_F5MUX=266
  • SLICEL_F6MUX=7
  • SLICEL_FAND=20
  • SLICEL_FFX=1097
  • SLICEL_FFY=887
  • SLICEL_G=2089
  • SLICEL_GAND=19
  • SLICEL_GNDF=227
  • SLICEL_GNDG=216
  • SLICEL_XORF=300
  • SLICEL_XORG=299
  • SLICEM=128
  • SLICEM_F=128
  • SLICEM_G=128
  • SLICEM_WSGEN=128
 
Configuration Data
BUFGMUX
  • S=[S_INV:5] [S:0]
BUFGMUX_GCLKMUX
  • DISABLE_ATTR=[LOW:5]
  • S=[S_INV:5] [S:0]
DCM
  • PSCLK=[PSCLK_INV:1] [PSCLK:1]
  • PSEN=[PSEN_INV:1] [PSEN:1]
  • PSINCDEC=[PSINCDEC_INV:1] [PSINCDEC:1]
  • RST=[RST:2] [RST_INV:0]
DCM_DCM
  • CLKDV_DIVIDE=[2:1] [16:1]
  • CLKOUT_PHASE_SHIFT=[NONE:2]
  • CLK_FEEDBACK=[1X:2]
  • DESKEW_ADJUST=[9:2]
  • DFS_FREQUENCY_MODE=[LOW:2]
  • DLL_FREQUENCY_MODE=[LOW:2]
  • DUTY_CYCLE_CORRECTION=[TRUE:2]
  • FACTORY_JF1=[0XC0:2]
  • FACTORY_JF2=[0X80:2]
  • PSCLK=[PSCLK_INV:1] [PSCLK:1]
  • PSEN=[PSEN_INV:1] [PSEN:1]
  • PSINCDEC=[PSINCDEC_INV:1] [PSINCDEC:1]
  • RST=[RST:2] [RST_INV:0]
IBUF_DELAY_ADJ_BBOX
  • DELAY_ADJ_ATTRBOX=[FIXED:4]
  • IBUF_DELAY_VALUE=[DLY0:4]
  • IFD_DELAY_VALUE=[DLY0:4]
  • SEL_IN=[SEL_IN:4] [SEL_IN_INV:0]
IBUF_PAD
  • IOATTRBOX=[LVCMOS25:4]
IOB
  • ICE=[ICE:16] [ICE_INV:0]
  • ICLK1=[ICLK1_INV:0] [ICLK1:16]
  • O1=[O1_INV:8] [O1:50]
  • T1=[T1_INV:16] [T1:0]
IOB_DELAY_ADJ_BBOX
  • DELAY_ADJ_ATTRBOX=[FIXED:16]
  • IBUF_DELAY_VALUE=[DLY0:16]
  • IFD_DELAY_VALUE=[DLY5:16]
  • SEL_IN=[SEL_IN:16] [SEL_IN_INV:0]
IOB_IFF1
  • CE=[CE:16] [CE_INV:0]
  • CK=[CK:16] [CK_INV:0]
  • IFF1_INIT_ATTR=[INIT0:16]
  • LATCH_OR_FF=[FF:16]
IOB_OUTBUF
  • IN=[IN_INV:8] [IN:50]
  • SUSPEND=[3STATE:58]
  • TRI=[TRI_INV:16] [TRI:0]
IOB_PAD
  • DRIVEATTRBOX=[12:58]
  • IOATTRBOX=[LVCMOS25:58]
  • SLEW=[SLOW:58]
MULT18X18SIO
  • CEA=[CEA_INV:0] [CEA:2]
  • CEB=[CEB_INV:0] [CEB:2]
  • CEP=[CEP:2] [CEP_INV:0]
  • CLK=[CLK:2] [CLK_INV:0]
  • RSTA=[RSTA:2] [RSTA_INV:0]
  • RSTB=[RSTB:2] [RSTB_INV:0]
  • RSTP=[RSTP_INV:0] [RSTP:2]
MULT18X18SIO_MULT18X18SIO
  • AREG=[1:2]
  • BREG=[1:2]
  • B_INPUT=[DIRECT:2]
  • CEA=[CEA_INV:0] [CEA:2]
  • CEB=[CEB_INV:0] [CEB:2]
  • CEP=[CEP:2] [CEP_INV:0]
  • CLK=[CLK:2] [CLK_INV:0]
  • PREG=[0:2]
  • PREG_CLKINVERSION=[0:2]
  • RSTA=[RSTA:2] [RSTA_INV:0]
  • RSTB=[RSTB:2] [RSTB_INV:0]
  • RSTP=[RSTP_INV:0] [RSTP:2]
RAMB16BWE
  • CLKA=[CLKA_INV:0] [CLKA:8]
  • CLKB=[CLKB_INV:0] [CLKB:8]
  • ENA=[ENA_INV:0] [ENA:8]
  • ENB=[ENB_INV:0] [ENB:8]
  • SSRA=[SSRA_INV:0] [SSRA:8]
  • SSRB=[SSRB_INV:0] [SSRB:8]
  • WEA0=[WEA0:8] [WEA0_INV:0]
  • WEA1=[WEA1:8] [WEA1_INV:0]
  • WEA2=[WEA2:8] [WEA2_INV:0]
  • WEA3=[WEA3_INV:0] [WEA3:8]
  • WEB0=[WEB0:8] [WEB0_INV:0]
  • WEB1=[WEB1:8] [WEB1_INV:0]
  • WEB2=[WEB2_INV:0] [WEB2:8]
  • WEB3=[WEB3:8] [WEB3_INV:0]
RAMB16BWE_RAMB16BWE
  • CLKA=[CLKA_INV:0] [CLKA:8]
  • CLKB=[CLKB_INV:0] [CLKB:8]
  • DATA_WIDTH_A=[4:8]
  • DATA_WIDTH_B=[4:8]
  • ENA=[ENA_INV:0] [ENA:8]
  • ENB=[ENB_INV:0] [ENB:8]
  • SSRA=[SSRA_INV:0] [SSRA:8]
  • SSRB=[SSRB_INV:0] [SSRB:8]
  • WEA0=[WEA0:8] [WEA0_INV:0]
  • WEA1=[WEA1:8] [WEA1_INV:0]
  • WEA2=[WEA2:8] [WEA2_INV:0]
  • WEA3=[WEA3_INV:0] [WEA3:8]
  • WEB0=[WEB0:8] [WEB0_INV:0]
  • WEB1=[WEB1:8] [WEB1_INV:0]
  • WEB2=[WEB2_INV:0] [WEB2:8]
  • WEB3=[WEB3:8] [WEB3_INV:0]
  • WRITE_MODE_A=[WRITE_FIRST:8]
  • WRITE_MODE_B=[WRITE_FIRST:8]
SLICEL
  • BX=[BX_INV:1] [BX:575]
  • BY=[BY:335] [BY_INV:6]
  • CE=[CE:990] [CE_INV:6]
  • CIN=[CIN_INV:0] [CIN:325]
  • CLK=[CLK:1216] [CLK_INV:2]
  • SR=[SR:980] [SR_INV:59]
SLICEL_CYMUXF
  • 0=[0:343] [0_INV:0]
  • 1=[1_INV:1] [1:342]
SLICEL_CYMUXG
  • 0=[0:328] [0_INV:0]
SLICEL_F5MUX
  • S0=[S0:266] [S0_INV:0]
SLICEL_F6MUX
  • S0=[S0:7] [S0_INV:0]
SLICEL_FFX
  • CE=[CE:895] [CE_INV:5]
  • CK=[CK:1095] [CK_INV:2]
  • D=[D:1097] [D_INV:0]
  • FFX_INIT_ATTR=[INIT0:1073] [INIT1:24]
  • FFX_SR_ATTR=[SRLOW:1080] [SRHIGH:17]
  • LATCH_OR_FF=[FF:1097]
  • REV=[REV_INV:0] [REV:1]
  • SR=[SR:899] [SR_INV:39]
  • SYNC_ATTR=[ASYNC:167] [SYNC:930]
SLICEL_FFY
  • CE=[CE:759] [CE_INV:4]
  • CK=[CK:886] [CK_INV:1]
  • D=[D:881] [D_INV:6]
  • FFY_INIT_ATTR=[INIT0:865] [INIT1:22]
  • FFY_SR_ATTR=[SRLOW:869] [SRHIGH:18]
  • LATCH_OR_FF=[FF:887]
  • SR=[SR:677] [SR_INV:46]
  • SYNC_ATTR=[ASYNC:176] [SYNC:711]
SLICEL_XORF
  • 1=[1_INV:1] [1:299]
SLICEM
  • BY=[BY:128] [BY_INV:0]
  • CLK=[CLK:128] [CLK_INV:0]
  • SR=[SR:128] [SR_INV:0]
SLICEM_F
  • DI=[DI:128] [DI_INV:0]
  • F_ATTR=[DUAL_PORT:128]
  • LUT_OR_MEM=[RAM:128]
SLICEM_G
  • DI=[DI:128] [DI_INV:0]
  • G_ATTR=[DUAL_PORT:128]
  • LUT_OR_MEM=[RAM:128]
SLICEM_WSGEN
  • CK=[CK:128] [CK_INV:0]
  • WE=[WE_INV:0] [WE:128]
 
Pin Data
BUFGMUX
  • I0=5
  • O=5
  • S=5
BUFGMUX_GCLKMUX
  • I0=5
  • OUT=5
  • S=5
BUFGMUX_GCLK_BUFFER
  • IN=5
  • OUT=5
DCM
  • CLK0=2
  • CLKFB=2
  • CLKFX=2
  • CLKIN=2
  • LOCKED=2
  • PSCLK=2
  • PSEN=2
  • PSINCDEC=2
  • RST=2
  • STATUS2=2
DCM_DCM
  • CLK0=2
  • CLKFB=2
  • CLKFX=2
  • CLKIN=2
  • LOCKED=2
  • PSCLK=2
  • PSEN=2
  • PSINCDEC=2
  • RST=2
  • STATUS2=2
IBUF
  • I=4
  • PAD=4
IBUF_DELAY_ADJ_BBOX
  • IBUF_OUT=4
  • SEL_IN=4
IBUF_INBUF
  • IN=4
  • OUT=4
IBUF_PAD
  • PAD=4
IOB
  • I=16
  • ICE=16
  • ICLK1=16
  • IQ1=16
  • O1=58
  • PAD=58
  • T1=16
IOB_DELAY_ADJ_BBOX
  • IBUF_OUT=16
  • IFD_OUT=16
  • SEL_IN=16
IOB_IFF1
  • CE=16
  • CK=16
  • D=16
  • Q=16
IOB_INBUF
  • IN=16
  • OUT=16
IOB_OUTBUF
  • IN=58
  • OUT=58
  • TRI=16
IOB_PAD
  • PAD=58
MULT18X18SIO
  • A0=2
  • A1=2
  • A10=2
  • A11=2
  • A12=2
  • A13=2
  • A14=2
  • A15=2
  • A16=2
  • A17=2
  • A2=2
  • A3=2
  • A4=2
  • A5=2
  • A6=2
  • A7=2
  • A8=2
  • A9=2
  • B0=2
  • B1=2
  • B10=2
  • B11=2
  • B12=2
  • B13=2
  • B14=2
  • B15=2
  • B16=2
  • B17=2
  • B2=2
  • B3=2
  • B4=2
  • B5=2
  • B6=2
  • B7=2
  • B8=2
  • B9=2
  • CEA=2
  • CEB=2
  • CEP=2
  • CLK=2
  • P0=2
  • P1=2
  • P10=2
  • P11=2
  • P12=2
  • P13=2
  • P14=2
  • P15=2
  • P16=2
  • P17=2
  • P18=2
  • P19=1
  • P2=2
  • P20=1
  • P3=2
  • P4=2
  • P5=2
  • P6=2
  • P7=2
  • P8=2
  • P9=2
  • RSTA=2
  • RSTB=2
  • RSTP=2
MULT18X18SIO_MULT18X18SIO
  • A0=2
  • A1=2
  • A10=2
  • A11=2
  • A12=2
  • A13=2
  • A14=2
  • A15=2
  • A16=2
  • A17=2
  • A2=2
  • A3=2
  • A4=2
  • A5=2
  • A6=2
  • A7=2
  • A8=2
  • A9=2
  • B0=2
  • B1=2
  • B10=2
  • B11=2
  • B12=2
  • B13=2
  • B14=2
  • B15=2
  • B16=2
  • B17=2
  • B2=2
  • B3=2
  • B4=2
  • B5=2
  • B6=2
  • B7=2
  • B8=2
  • B9=2
  • CEA=2
  • CEB=2
  • CEP=2
  • CLK=2
  • P0=2
  • P1=2
  • P10=2
  • P11=2
  • P12=2
  • P13=2
  • P14=2
  • P15=2
  • P16=2
  • P17=2
  • P18=2
  • P19=1
  • P2=2
  • P20=1
  • P3=2
  • P4=2
  • P5=2
  • P6=2
  • P7=2
  • P8=2
  • P9=2
  • RSTA=2
  • RSTB=2
  • RSTP=2
RAMB16BWE
  • ADDRA10=8
  • ADDRA11=8
  • ADDRA12=8
  • ADDRA13=8
  • ADDRA2=8
  • ADDRA3=8
  • ADDRA4=8
  • ADDRA5=8
  • ADDRA6=8
  • ADDRA7=8
  • ADDRA8=8
  • ADDRA9=8
  • ADDRB10=8
  • ADDRB11=8
  • ADDRB12=8
  • ADDRB13=8
  • ADDRB2=8
  • ADDRB3=8
  • ADDRB4=8
  • ADDRB5=8
  • ADDRB6=8
  • ADDRB7=8
  • ADDRB8=8
  • ADDRB9=8
  • CLKA=8
  • CLKB=8
  • DIB0=8
  • DIB1=8
  • DIB2=8
  • DIB3=8
  • DOA0=8
  • DOA1=8
  • DOA2=8
  • DOA3=8
  • DOB0=8
  • DOB1=8
  • DOB2=8
  • DOB3=8
  • ENA=8
  • ENB=8
  • SSRA=8
  • SSRB=8
  • WEA0=8
  • WEA1=8
  • WEA2=8
  • WEA3=8
  • WEB0=8
  • WEB1=8
  • WEB2=8
  • WEB3=8
RAMB16BWE_RAMB16BWE
  • ADDRA10=8
  • ADDRA11=8
  • ADDRA12=8
  • ADDRA13=8
  • ADDRA2=8
  • ADDRA3=8
  • ADDRA4=8
  • ADDRA5=8
  • ADDRA6=8
  • ADDRA7=8
  • ADDRA8=8
  • ADDRA9=8
  • ADDRB10=8
  • ADDRB11=8
  • ADDRB12=8
  • ADDRB13=8
  • ADDRB2=8
  • ADDRB3=8
  • ADDRB4=8
  • ADDRB5=8
  • ADDRB6=8
  • ADDRB7=8
  • ADDRB8=8
  • ADDRB9=8
  • CLKA=8
  • CLKB=8
  • DIB0=8
  • DIB1=8
  • DIB2=8
  • DIB3=8
  • DOA0=8
  • DOA1=8
  • DOA2=8
  • DOA3=8
  • DOB0=8
  • DOB1=8
  • DOB2=8
  • DOB3=8
  • ENA=8
  • ENB=8
  • SSRA=8
  • SSRB=8
  • WEA0=8
  • WEA1=8
  • WEA2=8
  • WEA3=8
  • WEB0=8
  • WEB1=8
  • WEB2=8
  • WEB3=8
SLICEL
  • BX=576
  • BY=341
  • CE=996
  • CIN=325
  • CLK=1218
  • COUT=328
  • F1=2135
  • F2=1975
  • F3=1632
  • F4=895
  • F5=14
  • FXINA=7
  • FXINB=7
  • G1=2085
  • G2=1934
  • G3=1562
  • G4=873
  • SR=1039
  • X=1388
  • XB=1
  • XQ=1097
  • Y=1332
  • YQ=887
SLICEL_C1VDD
  • 1=8
SLICEL_C2VDD
  • 1=7
SLICEL_CYMUXF
  • 0=343
  • 1=343
  • OUT=343
  • S0=343
SLICEL_CYMUXG
  • 0=328
  • 1=328
  • OUT=328
  • S0=328
SLICEL_F
  • A1=2127
  • A2=1975
  • A3=1632
  • A4=895
  • D=2137
SLICEL_F5MUX
  • F=266
  • G=266
  • OUT=266
  • S0=266
SLICEL_F6MUX
  • 0=7
  • 1=7
  • OUT=7
  • S0=7
SLICEL_FAND
  • 0=20
  • 1=20
  • O=20
SLICEL_FFX
  • CE=900
  • CK=1097
  • D=1097
  • Q=1097
  • REV=1
  • SR=938
SLICEL_FFY
  • CE=763
  • CK=887
  • D=887
  • Q=887
  • SR=723
SLICEL_G
  • A1=2076
  • A2=1932
  • A3=1562
  • A4=873
  • D=2089
SLICEL_GAND
  • 0=19
  • 1=19
  • O=19
SLICEL_GNDF
  • 0=227
SLICEL_GNDG
  • 0=216
SLICEL_XORF
  • 0=300
  • 1=300
  • O=300
SLICEL_XORG
  • 0=299
  • 1=299
  • O=299
SLICEM
  • BY=128
  • CLK=128
  • F1=128
  • F2=128
  • F3=128
  • F4=128
  • G1=128
  • G2=128
  • G3=128
  • G4=128
  • SR=128
  • X=128
SLICEM_F
  • A1=128
  • A2=128
  • A3=128
  • A4=128
  • D=128
  • DI=128
  • WF1=128
  • WF2=128
  • WF3=128
  • WF4=128
  • WS=128
SLICEM_G
  • A1=128
  • A2=128
  • A3=128
  • A4=128
  • DI=128
  • WG1=128
  • WG2=128
  • WG3=128
  • WG4=128
  • WS=128
SLICEM_WSGEN
  • CK=128
  • WE=128
  • WSF=128
  • WSG=128
 
Software Quality
Run Statistics
Bitgen 12913 12912 0 0 0 0 0
MAP 7042 6844 0 0 0 0 0
NGDBuild 7359 7343 0 0 0 0 0
PAR 6836 6484 322 0 0 0 0
Start 0 0 0 0 0 0 0
_impact 245 241 0 0 0 0 0
bitgen 1 1 0 0 0 0 0
edif2ngd 74898 74894 0 0 0 0 0
map 14 2 0 0 0 0 0
ngc2edif 140 140 0 0 0 0 0
ngcbuild 117 117 0 0 0 0 0
ngdbuild 17 16 0 0 0 0 0
par 2 2 0 0 0 0 0
trce 6490 6486 0 0 0 0 0
xst 7095 6992 0 0 0 0 0
 
Unisim Statistics
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_AND2=320 NGDBUILD_NUM_AND2B1=324 NGDBUILD_NUM_AND3=10 NGDBUILD_NUM_AND3B1=11
NGDBUILD_NUM_AND3B2=8 NGDBUILD_NUM_AND3B3=1 NGDBUILD_NUM_AND4=2 NGDBUILD_NUM_AND4B1=3
NGDBUILD_NUM_AND4B2=2 NGDBUILD_NUM_AND4B3=2 NGDBUILD_NUM_AND4B4=1 NGDBUILD_NUM_BUFG=5
NGDBUILD_NUM_DCM_SP=2 NGDBUILD_NUM_FD=14 NGDBUILD_NUM_FDC=6 NGDBUILD_NUM_FDCE=59
NGDBUILD_NUM_FDCPE=98 NGDBUILD_NUM_FDE=170 NGDBUILD_NUM_FDP=8 NGDBUILD_NUM_FDPE=4
NGDBUILD_NUM_FDR=323 NGDBUILD_NUM_FDRE=1346 NGDBUILD_NUM_FDRSE=1 NGDBUILD_NUM_FDS=1
NGDBUILD_NUM_FDSE=33 NGDBUILD_NUM_GND=22 NGDBUILD_NUM_IBUF=20 NGDBUILD_NUM_INV=27
NGDBUILD_NUM_LUT1=171 NGDBUILD_NUM_LUT1_L=122 NGDBUILD_NUM_LUT2=478 NGDBUILD_NUM_LUT2_L=145
NGDBUILD_NUM_LUT3=896 NGDBUILD_NUM_LUT3_L=509 NGDBUILD_NUM_LUT4=1101 NGDBUILD_NUM_LUT4_L=515
NGDBUILD_NUM_MULT18X18SIO=2 NGDBUILD_NUM_MULT_AND=39 NGDBUILD_NUM_MUXCY=13 NGDBUILD_NUM_MUXCY_L=658
NGDBUILD_NUM_MUXF5=266 NGDBUILD_NUM_MUXF6=7 NGDBUILD_NUM_NAND2=1 NGDBUILD_NUM_NOR2=5
NGDBUILD_NUM_OBUF=42 NGDBUILD_NUM_OBUFT=16 NGDBUILD_NUM_OR2=203 NGDBUILD_NUM_OR2B1=7
NGDBUILD_NUM_OR3=5 NGDBUILD_NUM_OR3B1=1 NGDBUILD_NUM_OR3B2=1 NGDBUILD_NUM_OR3B3=1
NGDBUILD_NUM_OR4=4 NGDBUILD_NUM_OR4B1=1 NGDBUILD_NUM_OR4B4=1 NGDBUILD_NUM_RAMB16BWE=8
NGDBUILD_NUM_VCC=14 NGDBUILD_NUM_XNOR2=14 NGDBUILD_NUM_XORCY=598