Getting Started with FPGA's - continued
Building an example FPGA project using Xilinx ISE and Altium Designer
With our generic white raster on the screen we can continue to build our test pattern circuit by adding a counter to the data input of the video controller. This time we will use a configurable counter that will cycle through all the various incremented colour data values that our display is capable of displaying. By selecting the counter from the Altium configurable devices library, we are able to right click on the placed device and set its configuration to what we require. In our case it will count in binary, have a carry flag to allow us to reset the counter when it hits 256, and provide a bus output for the 8 bits so a simple bus connection can be achieved to the video controller; as well as adding a reset pin and defining the clocking type. Once configured we add a few frequency dividers to generate a count clock before connecting the circuit up and testing it out.


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Remove the "VCC" symbol from the DATA[7..0] input on the video controller. From the FPGA configurable generic library, place a counter close to the video controller.
Right click on the counter and select "Configure". In the following dialogue box set the desired setting for the counter. Binary, Sync Reset, Count Up, Positive Clock, 8 bit and a bus output.
Now add a few dividers from the 14M clock and connect to the counters clock. A divider chain consisting of /256+/256+/128 gives a colour screen change of around 2 colour changes per second.
Again we get a picture, and sure enough the display shows each of the possible colours from Carte Blanches 2BPP video interface, cycling through at a rate of around 2 colour changes per second.


With the design complete, once again check for errors and save your work before bringing up the "Devices View" window. Click "Program FPGA" to begin compiling, synthesizing, building and programming the bit stream into Carte Blanche's FPGA.

In the last phase of our project we will construct a colour bar/cube generator using horizontal and vertical timers in conjuction with colour data. These will be multiplexed into the video graphics controller with sync and position timing information. The colour bars and their timing will be built using the generic timing information required by the VGA display and written asynchronously into the display controller. As a result, we should get a pretty good image if our timing is accurate. As this configuration has been built and proven many time before in other circuits, we will borrow the timing details from an existing design. This will allow us to simply place counters and multiplexers with known good timing data, allowing us to create the circuit quickly.



Remove the divider circuits and relocate the counter into an open area. Reconfigure the counter as binary, with async reset, up, positive clock, 16 bits and the output configured as a bus.
Copy and paste another counter accordingly. Add two inverters and configure as well. Connect the chip enables (CE) of the two counters to VCC.
Add wires and buses to connect up each circuit before adding nets using the illustration as a guide.
Add the video sync window logic and attach nets accordingly.
Place the multiplexers for blanking and video data. Configure the two devices accordingly.
Add wires and buses to connect up each circuit before adding nets according to the illustration.
We now have our completed circuit. Two multiplexers, one to define video data, the other for sync and blanking. We have the sync and blanking logic, used to detect sync windows, and the horizontal and vertical counters used to generate the sync position timing. With all devices plugged up, nets being correct, devices annotated, we are now ready to attempt to compile the design and see how it works.



The project compiled ok and downloaded the bitstream to our Carte Blanche. This time we get a somewhat more intelligent image. Showing each of the primary colours and a sample of each shade plus black and white. The image may be slightly offset, but this is because we are using asynchronous timing to blindly generate a video image with approximate intervals for sync and position. For the purpose of this exercise, this sort of interface is fine. From here, using a video memory, you can display any information you want with Carte Blanche, and using the read/address pixel data feedback, you can lock your image to be accurate and concise.

If you would like to download this project to compile and experiment with, you can do so from the Downloads section.