Altium designer is a software package for the IBM PC that attempts to provide all the required resources needed for complete product design in one unified environment. AD is the author's preferred choice, as it is a tool set that he has known since its inception (when Altium was known as Protel) and has had readily available access to. Although Carte Blanche utilises Altium Designer extensively, the area of the package that this guide will focus on is the FPGA and Embedded design aspects of the software only. It is recommended to review the tutorials regarding basic use of the package.
Getting Started with FPGA's
Building an example FPGA project using Xilinx ISE and Altium Designer
FPGA's in hardware designs enable a powerful and flexible design environment for developing Apple II/III products. There are several key design tool software packages available on the market to choose from to develop and generate a design code from. Choosing the tool that best suits you can be an important decision, as investing in the effort to learn a vendors tool usually means by the time you are fluent in its use, it has become an extension of your skill set. It is for this reason that stating one tool is better than another is difficult to do, as usually you need to be proficient in both tools to really know this. For tools based on the IBM PC, it is important to note that no tool is perfect. Learning the bugs in your chosen tool, how to avoid them and how to perform any particular task in several different ways are just some of the skills you need to master to ensure your tool never prevents you from achieving what you need in your design. This 'getting started' guide will go through setting up and running a Carte Blanche design using Xilinx ISE Webpack and Altium Designer S09.
In this example we will put together a simple hardware based video project that displays a raster before upgrading it to display colour bars on the screen. The project will be built using the Carte Blanche template as the foundation. The template can be downloaded from the downloads page and is suitable for both the 250E and 500E thanks to Altium's multi-target supporting environment. In this example we will select, layout, configure, compile, and download the design to the Carte Blanche board and see how it behaves on the screen. Ensure you have your Carte Blanche board plugged into your Apple, your JTAG Adaptor plugged in, and Altium Designer installed and registered on your PC.
Important: When using Xilinx Spartan 3E devices with Altium Designer, ensure the platform Flash is blank prior to downloading any .bit images. Erasing the Flash can be achieved using Xilinx ISE's Impact application. This requirement may be resolved in later releases of AD.
In preparation to start the design, follow the instructions below.
Using a very short cable and Altium's DT02 JTAG adaptor, plug up Carte Blanche's JTAG interface to the AD development environment.
Launch Altium Designer and open the CarteBlanche.PRJPCB from the renamed template folder.
Both Carte Blanche I 250 and 500's are able to utilise the same project template. The template folder consists of the setup information required to start designing with Carte Blanche without the need to configure the development environment or declare any hardware, as it is all provided. The template project contains the Carte Blanche Schematic for FPGA cross reference and a ready-to-go linked FPGA project for your design which includes common clocks, and a defined group of IO to select from. Also included are the FPGA constraint files, one for the 250 and one for 500, which are automatically selected by Altium Designer depending on which FPGAs AD finds at the end of your JTAG adaptor. If you have 2 Carte Blanches, either the same or of different types, AD is able to work with both cards simultaneously. This makes for fast turnaround of designs and easy generation of download code.
Within the project structure, double click on the FPGA project called CarteBlanche_FPGA. The Carte Blance FPGA project template will open.
You will now see the template file with the parked IO. The shaded items (Compiler Masked) disables what is beneath them. These turn off various IO's in different configurations keeping them dormant until we need them and thus not causing any errors. The exposed IO's are to be used as a simple "Tool chain Test".
Click on the "Devices" view tab to start the project building process. Click "Program FPGA". This will test the project to ensure that there are no problems or errors during the Compile, Synthesize, Build or Program phases prior to starting the project.
One of the key features of the AD environment is its ability to mix schematic and code. This top level abstract style of design makes the overall project easy to manage and navigate. In this example we will use schematic library items from various sources to piece together a design before compiling it into a bitstream suitable for download to the target FPGA on Carte Blanche. We will construct our video controller in hardware and confirm we can generate the correct timings, then add different colour rasters to the display before completing the design to display a hardware-based colour bar generator. Before we begin, we will test our tool chain to ensure we can compile, synthesize, build and program our FPGA successfully. You will notice in the Carte Blanche template file two unmasked services. These are pins 107 and 108 of Carte Blanche's FPGA. We have configured these to be outputs (the direction of the port symbol is pointing away from the wire and net) and we have set them to zero, or low, using GND symbols. This, although it utilises almost no FPGA resources, is a valid project, and perfect for testing the tool chain. Open up the devices view, connect to your target, and click "Program FPGA". Confirm the process flows through as it should and downloads to your Carte Blanche board successfully.
With the tool chain test passed successfully, we will now re-apply the compiler mask to turnoff the tool test IO. In our example, we will require an SVGA interface. Locate the SVGA interface and remove the compiler mask to enable its IO.
With the "Tool Chain" test working correctly, we can re-apply the "Compiler Mask" to turn it off.
Locate the VGA interface and remove its "Compiler Mask" to enable its IO's and nets.
Make a copy of the tracks and nets only before placing a pre-built video controller from the supplied Altium Libraries.
After placing the video controller from the libraries, connect up the Red, Green, Blue, and Sync IO's to the controller's corresponding IO. The next step is to provide a clock. The Video controller can produce a VGA complaint signal using a 25MHZ reference. To create this frequency, we will remove the compiler mask from our reference system clock of 14.31818MHz and connect it up to one of the FPGA's internal DCM clock managers to multiply it up by seven times. This gives us just over 100MHz. A further frequency divider gives us the required 25MHZ.
Connect up the Video Controller to its IO and place "No ERC markers on the unused I2C SDA and SCL pins".
Remove the compiler mask to enable the clock and its IO. Place a copy of the wire and net close to the video controller so we can plug up to it.
We will now place some more dividers and a few clock buffers. Clock buffers should be used on the source of any clock signals used in the design.
Now we connect it all up and make everything look tidy. Dont forget, its a proven scientific fact that tidy stuff works better! Note we have connected DATA[7..0] to VCC. According to the datasheet, this will drive 0xFF into the device, displaying the colour White for every pixel - producing a Raster.
The first stage of the design is complete, we are now ready to compile it and see if we get our white raster. The next step is to add some "In Chip" test equipment, so we can measure our frequencies, including the Horizontal and Vertical drive outputs to ensure we are within the VGA specification for our chosen mode. The extra 50MHZ clock in the design will provide a sample clock to our internal test equipment, which will report back to Altium Designer via the soft (or Nexus) JTAG chain.
As we will be using Soft JTAG to connect to our test gear, we will unmask the soft JTAG interface and enable the Nexus logic controller on Carte Blanche.
We now add two frequency counters from the "Test Instruments" library supplied with AD and connect them up to our primary frequencies as well as the video sync outputs.
After checking the design for assembly placement errors, we are now ready to attempt to build the project and download. Open up the "Devices View" dialogue, select your FPGA and hit "Program FPGA". On completion, you should see your test instruments on the screen.
Double clicking on each test instrument will bring up their information displays. With our test gear on screen, we can see the operating frequencies of the design. For a quick and dirty display controller, its not too bad. From our 14.31818MHz sys clock, we get a good 25MHz video reference. The Horizontal drive of 31Khz is spot on and Vertical drive is 2Hz short of being perfect. Now, the next step is to plug up a monitor to Carte Blanche's Video Port and see what is coming out.
The results are good. We have a solid lock for our Horizonal and Vertical Sync's, and all pixels are a clean consistant white. No shimmer or moire. The video controller is working as expected.
Now for the fun bit. To add a colour bar timing generator in hardware to feed the data input of the Video Controller with something a little more interesting.
