Other Tools for working with Carte Blanche Designs
Testing interfaces, Flash programmers and diagnostic tools for Carte Blanche's FPGA
Picoblaze is the term commonly given to Xilinx's FPGA utility program used for writing design configuration data to an FPGA's Flash memory. It is available from Xilinx as a configurable block of code and is based on Xilinx's Picoblaze soft core micro processor. Once configured, Picoblaze can be downloaded to the target FPGA, where it sets itself up to receive data and write it to Flash. Although Picoblaze is a lot slower in comparison, in a sense its similar to JAT's Flash programming option. The major advantage of Picoblaze is that it allows you to download configuration bitstreams via a TTL (5.0V) or CMOS (3.3V) UART Serial port via a USB port. Although this serial port is similar to what is commonly known as the COM port, or RS232 port of a PC, it is actually not compatible and operates at far lower voltages. Its important to note that although Carte Blanche has a standard serial port, Carte Blanche is unable to tolerate the RS232 +/-12V levels of a typical PC RS232 port directly.
Xilinx's Picoblaze has been prepared for Carte Blanche and is available from the downloads page for both the 250E and 500E. A cable to suit the TTL/CMOS requirements of a direct connection to the FPGA on Carte Blanche is available from several sources such as Dontronics (in Australia) Mouser or Digikey. The specification for a typical cable of this type can be downloaded from here. Although these cables only look like a USB connector with flying leads at one end, there is actually a USB to UART controller IC embedded in the boot of the connector. On installing the cable to your PC, the cable will become available as standard PC COM port, except at CMOS (3.3V) or TTL (5V) levels. In my example, my cable was assigned as COM3.
Picoblaze is available for Carte Blanche and may be used to write new images to Carte Blanche's Flash. To re-flash your card using Picoblaze, follow the instructions detailed below:
Plug the JTAG leads into CB's JTAG header as you would when you are performing any other JTAG activity. Note the two additional leads - The White and the Grey. These connect to the soft TCK and TDI respectively and are Picoblaze's TXD and RXD lines.
An additional lead connecting to the TTL USB cable is Ground. In the illustration above it is black, and on the left of the photo. You can connect this lead to any available ground point on Carte Blanche. I have chosen Pin 2 of J4. All GND pins of J4 have been circled on the PCB for easy identification.
Launch ISE's Impact program and open a new project.
Select "Configure device using Boundary Scan (JTAG)"
- JTAG is also know as IEEE 1149.1
Right click and choose "Setup cable...". Select your JTAG Adaptor. In my case, a Xilinx USB Cable.
Your FPGA should now appear on the screen, otherwise right click to "Initialize Chain...". Right click on the FPGA, select "Assign new file", select "PBP1xx0.bit".
Now right click again, this time select "Program..."
Although Picoblaze is complex and slow in comparison to to JAT, it is still a useful tool to have on hand in case a problem arises where other methods won't work as well. Picoblaze is a standard utility for many Spartan based platforms and is common amongst Xilinx FPGA developers. However, Carte Blanche is lucky enough to have Alex's JAT application, which for most situations is superior and a more suitable choice for upgrading and re-flashing Carte Blanche boards in a very short time.
Picoblaze receives configuration bitstream data from a PC via a USB to TTL UART cable (either 3.3v or 5v version) These cables directly interface the PC's USB accessible virtual serial port to the FPGA on Carte Blanche via the Soft JTAG interface, bypassing the PC's aggressive RS232 COM ports.
Picoblaze downloads to the target FPGA where it builds a framework and menu driven system to allow the user to download and manage host Flash memories for storing configuration bitstreams.
Prepare the Flash ready for programming by typing "E" for Erase. You will be prompted if you are sure you wish to continue. Type uppercase "Y" to confirm and proceed. On the program's return, the Flash should now be erased.
It is important to confirm the Flash has been fully erased. If the Flash is not completely blank, it will result in a corrupt image being written to the device. To confirm our Flash is truly blank, type "R", then enter the address of "000000". A blank flash will display a page of "FF"'s.
Picoblaze will now receive the file from the local PC and write it to Flash memory. Depending on the size of the device will determine how long it will take to complete. On completion of the programming phase, Picoblaze will respond with the last address and an "OK". Programming is now done.
As a cross check to confirm the information has actually been written to flash, press "R" and type in address "000000". This time we should see several key bytes written into the first few blocks of the device.
Power-cycle your Apple to restart the FPGA and confirm the green "DONE" LED on Carte Blanche illuminates. This visual indicator confirms the FPGA loaded the new Bitstream correctly.
If you are in a position where you have two Carte Blanche Cards, then the option to download from one card to the other is possible (I say possible, as this has not been completed as yet). This involves reassigning the Video Interface to a JTAG interface and downloading JTAG data to the target board using a standard JTAG cable between the two connectors on each card. The concept is based on the ability to allow one Carte Blanche to dynamically reconfigure another on demand whilst managing interaction with the Apple II. This is intended for use in designs such as JAMMA and MAME style hardware based video games as well as dynamic Apple peripheral boards.
Carte Blanche to Carte Blanche: As a subtask, one CB manages interaction with the AII, whilst reconfiguring the other CB with new hardware designs at high speed.
The most ideal setup for for Carte Blanche hardware programming is to have an in-system JTAG adaptor - enabling true in-system on the fly reconfiguration of any Carte Blanche cards. Each card can be daisy-chained allowing all FPGA's to be recognised by the Apple and its OS. However, the concern is the Apple's ability to write the configuration data fast enough. Considering the balance of easy interface and speed, an experimental JTAG adaptor has been made to suit the Apple Games port. This adaptor utilizes AN0, AN1 and AN2, along with PB2 to emulate a JTAG interface of TDI, TDO, TCK and TMS. It does not affect the external Games port functionality. The adaptor will be trialled soon, and if all goes well and it works suitably (even as an emergency backup programming device), then we will organise to make the board available to anyone who would like to use it.
In-System programming. Building hardware peripheral boards on the fly. The Apple II Games Port JTAG adaptor interfaces to Carte Blanche's JTAG port providing level translation and Data IO.
