Experimenting with Carte Blanche and a JTAG Adaptor
Dynamically downloading designs into your Carte Blanche whilst preserving its on-board Flash
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Carte Blanche's onboard JTAG interface consists of three parts. 1. A Hard JTAG chain, or standard JTAG, which is used to interface directly and exclusively to the Xilinx FPGA.  2. A Soft JTAG chain, which interfaces to general purpose IO of the FPGA and is used as a private communications link to peripherals built inside the FPGA, that may require outside world communcations. Such devices are memory controllers, for altering the content of memory outside of the design. Logic analysers, for reporting information and data back to an external test tool. Console style UARTS, typically used as a standard "out-of-band" style COM port for configuration data and access to the internal operations of the design, such as break points and registers. 3. A Ground reference and a signal reference. In the case of Carte Blanche, our Ground reference is Ground (or 0v), and our signalling voltage reference is 3.3V.
Carte Blanche is capable of not only becoming an Apple II peripheral, but also operates as a complex device interfaced to the Apple via its bus, or a complete independent system on the chip, such as several Apple's operating in parallel to the host Apple. The best way to get a feel for how it all works is to locate a few examples in the download section and and download them into Carte Blanche using your JTAG setup, and see what they do. This method is safe, as it does not write to the Flash on CB, as it only uploads its configuration data to the FPGA exclusively. It is recommended however not to have a floppy or hard disk connected to your system when working this way, as it is possible for rogue or unknown behaviour to cause Carte Blanche to communicate over the Apple bus in a sporadic way, possibly causing corruption to other writeable media devices connected to the system.

The examples and diagnostics on the download page are a good place to start. Downloading the SVGA test apps illustrates that Carte Blanche is capable of higher resolutions than those the Apple can provide. It also demonstrates the obvious changes between one hardware design and another. Other examples, such as the Alarm clock, show how building your own chip with full functionality and control registers can be realised with CB and the IIe bus.

Downloading code dynamically using Xilinx's Impact application is detailed below.






Plug the JTAG leads into CB's header. The JTAG pins are marked on CB's PCB and the cable. Match each of the TDI, TDO TCK ,TMS, GND and REF(3V3) pins for a JTAG connection and power on. The LED on the JTAG adaptor should go green.








Head to the download page and download a few examples to suit your FPGA.







Launch ISE's Impact program and open a new project








Select "Configure device using Boundary Scan (JTAG)"
- JTAG is also know as IEEE 1149.1









Right click and choose "Setup cable...". Select your JTAG Adaptor. In my case, a Xilinx USB Cable







Your FPGA should now appear on the screen, otherwise right click to "Initalize Chain...". Right click on the FPGA, select "Assign new file", select "VGA1_250.bit".
Now right click again, this time select "Program..."








Your Carte Blanche FPGA should now be programmed with the VGA1_250 diagnostic design with the display running on the Apple IIe's screen. This method only programs the FPGA, not the Flash. So downloading different configuration files consecutively does not affect your Carte Blanche as a JAT card. This method is ideal for "Reviewing" a configuration to determine its suitability prior to Flashing. If you wish to actually turn Carte Blanche into a VGA1_250 configured board, simply copy the .BIT onto an SD card and ask JAT to write it to Flash. IMPORTANT: Once JAT has been erased or overwritten, there will be no option for in-system programming. To replace the Flash again, you will have to go through the procedure for "What to do if my Carte Blanche Flash is corrupted"
On each Carte Blanche, the JTAG interface has each pin clearly marked. Interfacing to the DLC series adaptors only requires HARD+REF to be connected.
JTAG, consists of TDI, TDO, TMS and TCK. The REF pins are GND and 3V3. Both CB and the Xilinx cable have the pins clearly marked for a one-to-one connection.
The VGA1 Carte Blanche diagnostic download. Designed using Altium's powerful high level library items, this diagnostic tests the FPGA's ability to implement several different Video controllers all operating independently of each other with a common host. Using "Peek" and "Poke" from the Apple II, the user can move the mouse cursor, select and move any of the windows.